Sowjanya Komatineni b4f99176a5 arm64: tegra: Fix SOR powergate clocks and reset ... Tegra210 device tree lists CSI clock and reset under SOR powergate node. But Tegra210 has CSICIL in SOR partition and CSI in VENC partition. So, this patch includes fix for SOR powergate node. Signed-off-by: Sowjanya Komatineni <skomatineni@nvidia.com> Signed-off-by: Thierry Reding <treding@nvidia.com>		2020-05-20 15:26:09 +02:00
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dts	arm64: tegra: Fix SOR powergate clocks and reset	2020-05-20 15:26:09 +02:00
.gitignore	.gitignore: add SPDX License Identifier	2020-03-25 11:50:48 +01:00
install.sh
Makefile	arm64: kbuild: remove compressed images on 'make ARCH=arm64 (dist)clean'	2020-01-21 16:28:36 +00:00