mirror of
https://github.com/AuxXxilium/linux_dsm_epyc7002.git
synced 2024-12-14 10:36:49 +07:00
6227e9f0e9
Now when we have properly working performance counters in nSIM
even with interrupt support (fix should be a part of upcoming
nSIM engineering build 2016.12-005) we may enable perf support
by default for all platforms that use nSIM for ARC cores simulation.
Note 1: PCT node was missing for some reason in nsimosci.dts
while all other nSIM-related .dts files already had
PCT node for quite some time, so adding it now.
Note 2: All defconfigs were regenerated with "make savedefconfig"
which led to some clean-ups in nsimosci_hs_smp_defconfig:
CONFIG_FRAMEBUFFER_CONSOLE=y was removed because it is
automatically selected now by DRM.
Signed-off-by: Alexey Brodkin <abrodkin@synopsys.com>
Signed-off-by: Vineet Gupta <vgupta@synopsys.com>
126 lines
3.0 KiB
Plaintext
126 lines
3.0 KiB
Plaintext
/*
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* Copyright (C) 2013-15 Synopsys, Inc. (www.synopsys.com)
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*/
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/*
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* Device tree for AXC001 770D/EM6/AS221 CPU card
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* Note that this file only supports the 770D CPU
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*/
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/include/ "skeleton.dtsi"
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/ {
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compatible = "snps,arc";
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#address-cells = <1>;
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#size-cells = <1>;
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cpu_card {
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compatible = "simple-bus";
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#address-cells = <1>;
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#size-cells = <1>;
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ranges = <0x00000000 0xf0000000 0x10000000>;
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core_clk: core_clk {
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#clock-cells = <0>;
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compatible = "fixed-clock";
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clock-frequency = <750000000>;
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};
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core_intc: arc700-intc@cpu {
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compatible = "snps,arc700-intc";
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interrupt-controller;
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#interrupt-cells = <1>;
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};
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/*
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* this GPIO block ORs all interrupts on CPU card (creg,..)
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* to uplink only 1 IRQ to ARC core intc
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*/
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dw-apb-gpio@0x2000 {
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compatible = "snps,dw-apb-gpio";
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reg = < 0x2000 0x80 >;
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#address-cells = <1>;
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#size-cells = <0>;
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ictl_intc: gpio-controller@0 {
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compatible = "snps,dw-apb-gpio-port";
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gpio-controller;
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#gpio-cells = <2>;
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snps,nr-gpios = <30>;
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reg = <0>;
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interrupt-controller;
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#interrupt-cells = <2>;
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interrupt-parent = <&core_intc>;
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interrupts = <15>;
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};
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};
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debug_uart: dw-apb-uart@0x5000 {
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compatible = "snps,dw-apb-uart";
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reg = <0x5000 0x100>;
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clock-frequency = <33333000>;
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interrupt-parent = <&ictl_intc>;
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interrupts = <19 4>;
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baud = <115200>;
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reg-shift = <2>;
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reg-io-width = <4>;
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};
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arcpct0: pct {
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compatible = "snps,arc700-pct";
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};
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};
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/*
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* This INTC is actually connected to DW APB GPIO
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* which acts as a wire between MB INTC and CPU INTC.
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* GPIO INTC is configured in platform init code
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* and here we mimic direct connection from MB INTC to
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* CPU INTC, thus we set "interrupts = <7>" instead of
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* "interrupts = <12>"
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*
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* This intc actually resides on MB, but we move it here to
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* avoid duplicating the MB dtsi file given that IRQ from
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* this intc to cpu intc are different for axs101 and axs103
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*/
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mb_intc: dw-apb-ictl@0xe0012000 {
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#interrupt-cells = <1>;
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compatible = "snps,dw-apb-ictl";
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reg = < 0xe0012000 0x200 >;
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interrupt-controller;
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interrupt-parent = <&core_intc>;
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interrupts = < 7 >;
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};
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memory {
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#address-cells = <1>;
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#size-cells = <1>;
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ranges = <0x00000000 0x80000000 0x20000000>;
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device_type = "memory";
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reg = <0x80000000 0x1b000000>; /* (512 - 32) MiB */
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};
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reserved-memory {
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#address-cells = <1>;
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#size-cells = <1>;
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ranges;
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/*
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* We just move frame buffer area to the very end of
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* available DDR. And even though in case of ARC770 there's
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* no strict requirement for a frame-buffer to be in any
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* particular location it allows us to use the same
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* base board's DT node for ARC PGU as for ARc HS38.
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*/
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frame_buffer: frame_buffer@9e000000 {
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compatible = "shared-dma-pool";
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reg = <0x9e000000 0x2000000>;
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no-map;
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};
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};
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};
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