mirror of
https://github.com/AuxXxilium/linux_dsm_epyc7002.git
synced 2024-11-30 10:06:43 +07:00
4ff4ae1258
Add the controller node, pinctrl settings for the customizable pins and sort the controllers like on rk3288 as emmc, sdmmc, sdio for handling convenience. Signed-off-by: Heiko Stuebner <heiko@sntech.de>
499 lines
11 KiB
Plaintext
499 lines
11 KiB
Plaintext
/*
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* Copyright (c) 2013 MundoReader S.L.
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* Author: Heiko Stuebner <heiko@sntech.de>
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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#include <dt-bindings/gpio/gpio.h>
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#include <dt-bindings/pinctrl/rockchip.h>
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#include <dt-bindings/clock/rk3066a-cru.h>
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#include "rk3xxx.dtsi"
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/ {
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compatible = "rockchip,rk3066a";
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cpus {
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#address-cells = <1>;
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#size-cells = <0>;
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enable-method = "rockchip,rk3066-smp";
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cpu@0 {
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device_type = "cpu";
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compatible = "arm,cortex-a9";
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next-level-cache = <&L2>;
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reg = <0x0>;
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};
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cpu@1 {
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device_type = "cpu";
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compatible = "arm,cortex-a9";
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next-level-cache = <&L2>;
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reg = <0x1>;
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};
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};
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sram: sram@10080000 {
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compatible = "mmio-sram";
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reg = <0x10080000 0x10000>;
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#address-cells = <1>;
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#size-cells = <1>;
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ranges = <0 0x10080000 0x10000>;
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smp-sram@0 {
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compatible = "rockchip,rk3066-smp-sram";
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reg = <0x0 0x50>;
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};
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};
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cru: clock-controller@20000000 {
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compatible = "rockchip,rk3066a-cru";
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reg = <0x20000000 0x1000>;
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rockchip,grf = <&grf>;
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#clock-cells = <1>;
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#reset-cells = <1>;
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};
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timer@2000e000 {
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compatible = "snps,dw-apb-timer-osc";
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reg = <0x2000e000 0x100>;
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interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&cru SCLK_TIMER2>, <&cru PCLK_TIMER2>;
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clock-names = "timer", "pclk";
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};
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timer@20038000 {
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compatible = "snps,dw-apb-timer-osc";
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reg = <0x20038000 0x100>;
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interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&cru SCLK_TIMER0>, <&cru PCLK_TIMER0>;
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clock-names = "timer", "pclk";
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};
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timer@2003a000 {
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compatible = "snps,dw-apb-timer-osc";
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reg = <0x2003a000 0x100>;
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interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&cru SCLK_TIMER1>, <&cru PCLK_TIMER1>;
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clock-names = "timer", "pclk";
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};
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pinctrl: pinctrl {
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compatible = "rockchip,rk3066a-pinctrl";
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rockchip,grf = <&grf>;
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#address-cells = <1>;
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#size-cells = <1>;
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ranges;
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gpio0: gpio0@20034000 {
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compatible = "rockchip,gpio-bank";
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reg = <0x20034000 0x100>;
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interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&cru PCLK_GPIO0>;
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gpio-controller;
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#gpio-cells = <2>;
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interrupt-controller;
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#interrupt-cells = <2>;
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};
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gpio1: gpio1@2003c000 {
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compatible = "rockchip,gpio-bank";
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reg = <0x2003c000 0x100>;
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interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&cru PCLK_GPIO1>;
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gpio-controller;
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#gpio-cells = <2>;
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interrupt-controller;
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#interrupt-cells = <2>;
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};
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gpio2: gpio2@2003e000 {
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compatible = "rockchip,gpio-bank";
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reg = <0x2003e000 0x100>;
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interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&cru PCLK_GPIO2>;
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gpio-controller;
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#gpio-cells = <2>;
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interrupt-controller;
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#interrupt-cells = <2>;
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};
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gpio3: gpio3@20080000 {
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compatible = "rockchip,gpio-bank";
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reg = <0x20080000 0x100>;
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interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&cru PCLK_GPIO3>;
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gpio-controller;
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#gpio-cells = <2>;
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interrupt-controller;
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#interrupt-cells = <2>;
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};
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gpio4: gpio4@20084000 {
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compatible = "rockchip,gpio-bank";
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reg = <0x20084000 0x100>;
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interrupts = <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&cru PCLK_GPIO4>;
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gpio-controller;
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#gpio-cells = <2>;
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interrupt-controller;
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#interrupt-cells = <2>;
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};
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gpio6: gpio6@2000a000 {
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compatible = "rockchip,gpio-bank";
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reg = <0x2000a000 0x100>;
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interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&cru PCLK_GPIO6>;
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gpio-controller;
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#gpio-cells = <2>;
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interrupt-controller;
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#interrupt-cells = <2>;
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};
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pcfg_pull_default: pcfg_pull_default {
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bias-pull-pin-default;
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};
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pcfg_pull_none: pcfg_pull_none {
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bias-disable;
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};
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emmc {
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emmc_clk: emmc-clk {
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rockchip,pins = <RK_GPIO3 31 RK_FUNC_2 &pcfg_pull_default>;
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};
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emmc_cmd: emmc-cmd {
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rockchip,pins = <RK_GPIO4 9 RK_FUNC_2 &pcfg_pull_default>;
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};
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emmc_rst: emmc-rst {
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rockchip,pins = <RK_GPIO4 10 RK_FUNC_2 &pcfg_pull_default>;
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};
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/*
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* The data pins are shared between nandc and emmc and
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* not accessible through pinctrl. Also they should've
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* been already set correctly by firmware, as
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* flash/emmc is the boot-device.
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*/
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};
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i2c0 {
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i2c0_xfer: i2c0-xfer {
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rockchip,pins = <RK_GPIO2 28 RK_FUNC_1 &pcfg_pull_none>,
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<RK_GPIO2 29 RK_FUNC_1 &pcfg_pull_none>;
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};
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};
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i2c1 {
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i2c1_xfer: i2c1-xfer {
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rockchip,pins = <RK_GPIO2 30 RK_FUNC_1 &pcfg_pull_none>,
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<RK_GPIO2 31 RK_FUNC_1 &pcfg_pull_none>;
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};
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};
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i2c2 {
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i2c2_xfer: i2c2-xfer {
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rockchip,pins = <RK_GPIO3 0 RK_FUNC_1 &pcfg_pull_none>,
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<RK_GPIO3 1 RK_FUNC_1 &pcfg_pull_none>;
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};
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};
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i2c3 {
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i2c3_xfer: i2c3-xfer {
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rockchip,pins = <RK_GPIO3 2 RK_FUNC_2 &pcfg_pull_none>,
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<RK_GPIO3 3 RK_FUNC_2 &pcfg_pull_none>;
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};
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};
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i2c4 {
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i2c4_xfer: i2c4-xfer {
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rockchip,pins = <RK_GPIO3 4 RK_FUNC_1 &pcfg_pull_none>,
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<RK_GPIO3 5 RK_FUNC_1 &pcfg_pull_none>;
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};
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};
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pwm0 {
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pwm0_out: pwm0-out {
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rockchip,pins = <RK_GPIO0 3 RK_FUNC_1 &pcfg_pull_none>;
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};
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};
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pwm1 {
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pwm1_out: pwm1-out {
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rockchip,pins = <RK_GPIO0 4 RK_FUNC_1 &pcfg_pull_none>;
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};
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};
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pwm2 {
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pwm2_out: pwm2-out {
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rockchip,pins = <RK_GPIO0 30 RK_FUNC_1 &pcfg_pull_none>;
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};
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};
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pwm3 {
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pwm3_out: pwm3-out {
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rockchip,pins = <RK_GPIO0 31 RK_FUNC_1 &pcfg_pull_none>;
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};
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};
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spi0 {
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spi0_clk: spi0-clk {
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rockchip,pins = <RK_GPIO1 5 RK_FUNC_2 &pcfg_pull_default>;
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};
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spi0_cs0: spi0-cs0 {
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rockchip,pins = <RK_GPIO1 4 RK_FUNC_2 &pcfg_pull_default>;
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};
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spi0_tx: spi0-tx {
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rockchip,pins = <RK_GPIO1 7 RK_FUNC_2 &pcfg_pull_default>;
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};
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spi0_rx: spi0-rx {
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rockchip,pins = <RK_GPIO1 6 RK_FUNC_2 &pcfg_pull_default>;
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};
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spi0_cs1: spi0-cs1 {
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rockchip,pins = <RK_GPIO4 15 RK_FUNC_1 &pcfg_pull_default>;
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};
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};
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spi1 {
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spi1_clk: spi1-clk {
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rockchip,pins = <RK_GPIO2 19 RK_FUNC_2 &pcfg_pull_default>;
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};
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spi1_cs0: spi1-cs0 {
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rockchip,pins = <RK_GPIO2 20 RK_FUNC_2 &pcfg_pull_default>;
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};
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spi1_rx: spi1-rx {
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rockchip,pins = <RK_GPIO2 22 RK_FUNC_2 &pcfg_pull_default>;
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};
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spi1_tx: spi1-tx {
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rockchip,pins = <RK_GPIO2 21 RK_FUNC_2 &pcfg_pull_default>;
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};
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spi1_cs1: spi1-cs1 {
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rockchip,pins = <RK_GPIO2 23 RK_FUNC_2 &pcfg_pull_default>;
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};
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};
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uart0 {
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uart0_xfer: uart0-xfer {
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rockchip,pins = <RK_GPIO1 0 RK_FUNC_1 &pcfg_pull_default>,
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<RK_GPIO1 1 RK_FUNC_1 &pcfg_pull_default>;
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};
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uart0_cts: uart0-cts {
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rockchip,pins = <RK_GPIO1 2 RK_FUNC_1 &pcfg_pull_default>;
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};
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uart0_rts: uart0-rts {
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rockchip,pins = <RK_GPIO1 3 RK_FUNC_1 &pcfg_pull_default>;
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};
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};
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uart1 {
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uart1_xfer: uart1-xfer {
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rockchip,pins = <RK_GPIO1 4 RK_FUNC_1 &pcfg_pull_default>,
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<RK_GPIO1 5 RK_FUNC_1 &pcfg_pull_default>;
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};
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uart1_cts: uart1-cts {
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rockchip,pins = <RK_GPIO1 6 RK_FUNC_1 &pcfg_pull_default>;
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};
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uart1_rts: uart1-rts {
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rockchip,pins = <RK_GPIO1 7 RK_FUNC_1 &pcfg_pull_default>;
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};
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};
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uart2 {
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uart2_xfer: uart2-xfer {
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rockchip,pins = <RK_GPIO1 8 RK_FUNC_1 &pcfg_pull_default>,
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<RK_GPIO1 9 RK_FUNC_1 &pcfg_pull_default>;
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};
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/* no rts / cts for uart2 */
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};
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uart3 {
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uart3_xfer: uart3-xfer {
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rockchip,pins = <RK_GPIO3 27 RK_FUNC_1 &pcfg_pull_default>,
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<RK_GPIO3 28 RK_FUNC_1 &pcfg_pull_default>;
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};
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uart3_cts: uart3-cts {
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rockchip,pins = <RK_GPIO3 29 RK_FUNC_1 &pcfg_pull_default>;
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};
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uart3_rts: uart3-rts {
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rockchip,pins = <RK_GPIO3 30 RK_FUNC_1 &pcfg_pull_default>;
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};
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};
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sd0 {
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sd0_clk: sd0-clk {
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rockchip,pins = <RK_GPIO3 8 RK_FUNC_1 &pcfg_pull_default>;
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};
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sd0_cmd: sd0-cmd {
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rockchip,pins = <RK_GPIO3 9 RK_FUNC_1 &pcfg_pull_default>;
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};
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sd0_cd: sd0-cd {
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rockchip,pins = <RK_GPIO3 14 RK_FUNC_1 &pcfg_pull_default>;
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};
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sd0_wp: sd0-wp {
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rockchip,pins = <RK_GPIO3 15 RK_FUNC_1 &pcfg_pull_default>;
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};
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sd0_bus1: sd0-bus-width1 {
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rockchip,pins = <RK_GPIO3 10 RK_FUNC_1 &pcfg_pull_default>;
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};
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sd0_bus4: sd0-bus-width4 {
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rockchip,pins = <RK_GPIO3 10 RK_FUNC_1 &pcfg_pull_default>,
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<RK_GPIO3 11 RK_FUNC_1 &pcfg_pull_default>,
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<RK_GPIO3 12 RK_FUNC_1 &pcfg_pull_default>,
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<RK_GPIO3 13 RK_FUNC_1 &pcfg_pull_default>;
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};
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};
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sd1 {
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sd1_clk: sd1-clk {
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rockchip,pins = <RK_GPIO3 21 RK_FUNC_1 &pcfg_pull_default>;
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};
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sd1_cmd: sd1-cmd {
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rockchip,pins = <RK_GPIO3 16 RK_FUNC_1 &pcfg_pull_default>;
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};
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sd1_cd: sd1-cd {
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rockchip,pins = <RK_GPIO3 22 RK_FUNC_1 &pcfg_pull_default>;
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};
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sd1_wp: sd1-wp {
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rockchip,pins = <RK_GPIO3 23 RK_FUNC_1 &pcfg_pull_default>;
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};
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sd1_bus1: sd1-bus-width1 {
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rockchip,pins = <RK_GPIO3 17 RK_FUNC_1 &pcfg_pull_default>;
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};
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sd1_bus4: sd1-bus-width4 {
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rockchip,pins = <RK_GPIO3 17 RK_FUNC_1 &pcfg_pull_default>,
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<RK_GPIO3 18 RK_FUNC_1 &pcfg_pull_default>,
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<RK_GPIO3 19 RK_FUNC_1 &pcfg_pull_default>,
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<RK_GPIO3 20 RK_FUNC_1 &pcfg_pull_default>;
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};
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};
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};
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};
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&i2c0 {
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pinctrl-names = "default";
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pinctrl-0 = <&i2c0_xfer>;
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};
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&i2c1 {
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pinctrl-names = "default";
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pinctrl-0 = <&i2c1_xfer>;
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};
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&i2c2 {
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pinctrl-names = "default";
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pinctrl-0 = <&i2c2_xfer>;
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};
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&i2c3 {
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pinctrl-names = "default";
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pinctrl-0 = <&i2c3_xfer>;
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};
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&i2c4 {
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pinctrl-names = "default";
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pinctrl-0 = <&i2c4_xfer>;
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};
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&mmc0 {
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pinctrl-names = "default";
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pinctrl-0 = <&sd0_clk &sd0_cmd &sd0_cd &sd0_bus4>;
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};
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&mmc1 {
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pinctrl-names = "default";
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pinctrl-0 = <&sd1_clk &sd1_cmd &sd1_cd &sd1_bus4>;
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};
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&pwm0 {
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pinctrl-names = "default";
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pinctrl-0 = <&pwm0_out>;
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};
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&pwm1 {
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pinctrl-names = "default";
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pinctrl-0 = <&pwm1_out>;
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};
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&pwm2 {
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pinctrl-names = "default";
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pinctrl-0 = <&pwm2_out>;
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};
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&pwm3 {
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pinctrl-names = "default";
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pinctrl-0 = <&pwm3_out>;
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};
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&spi0 {
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pinctrl-names = "default";
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pinctrl-0 = <&spi0_clk &spi0_tx &spi0_rx &spi0_cs0>;
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};
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&spi1 {
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pinctrl-names = "default";
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pinctrl-0 = <&spi1_clk &spi1_tx &spi1_rx &spi1_cs0>;
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};
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&uart0 {
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pinctrl-names = "default";
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pinctrl-0 = <&uart0_xfer>;
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};
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&uart1 {
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pinctrl-names = "default";
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pinctrl-0 = <&uart1_xfer>;
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};
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&uart2 {
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pinctrl-names = "default";
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pinctrl-0 = <&uart2_xfer>;
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};
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&uart3 {
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pinctrl-names = "default";
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pinctrl-0 = <&uart3_xfer>;
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};
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&wdt {
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compatible = "rockchip,rk3066-wdt", "snps,dw-wdt";
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};
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