Deepak M b426f98515 drm/i915/glk: Program new MIPI DSI PHY registers for GLK ... Program the clk lane and tlpx time count registers to configure DSI PHY. v2: Addressed Jani's Review comments(renamed bit field macros) v3: Program clk lane timing reg same as dphy param reg. v4: Removed "line over 80 character" warning Signed-off-by: Deepak M <m.deepak@intel.com> Signed-off-by: Madhav Chauhan <madhav.chauhan@intel.com> Reviewed-by: Jani Nikula <jani.nikula@intel.com> Signed-off-by: Jani Nikula <jani.nikula@intel.com> Link: http://patchwork.freedesktop.org/patch/msgid/1487335415-14766-3-git-send-email-madhav.chauhan@intel.com		2017-02-28 11:31:17 +02:00
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drm	drm/i915/glk: Program new MIPI DSI PHY registers for GLK	2017-02-28 11:31:17 +02:00
host1x	gpu: host1x: Set OF node for new host1x devices	2017-01-30 11:47:44 +01:00
ipu-v3	gpu: ipu-v3: Stop overwriting pdev->dev.of_node of child devices	2017-02-17 08:04:27 +01:00
vga	vgaarb: use valid dev pointer in vgaarb_info()	2016-11-22 16:40:35 +01:00
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