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https://github.com/AuxXxilium/linux_dsm_epyc7002.git
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edc30077c9
Debugging eMMC on upstream kernels it has been noticed that when the targetpack configures MMC0 clock to 200Mhz (required to switch to HS200) then everything works OK. However if the kernel sets the clock rate using clk_set_rate, then the eMMC card initialisation fails with timeouts. Lower clock speeds (the default being 50Mhz) work ok, but they we fail to get good eMMC transfer rates. Looking through the vendor kernel clock driver reveals Giuseppe had already fixed this issue, but the patch hasn't made its way upstream. The issue is fixed by changing the logic to manage the pdiv and fdiv divisors used for setting the rate inside the flexgen driver code. Pdiv is mainly targeted for low freq results, while fdiv should be used for divs =< 64. The other way can lead to 'duty cycle' issues. I have changed the original patch to keep the original behaviour in cases where the div is >64 which matches the original comment and patch description more closely. Although no clocks appear to hit this case currently when booting an upstream kernel. Signed-off-by: Peter Griffin <peter.griffin@linaro.org> Signed-off-by: Giuseppe Cavallaro <peppe.cavallaro@st.com> Signed-off-by: Michael Turquette <mturquette@linaro.org> |
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| .. | ||
| clk-flexgen.c | ||
| clkgen-fsyn.c | ||
| clkgen-mux.c | ||
| clkgen-pll.c | ||
| clkgen.h | ||
| Makefile | ||