mirror of
https://github.com/AuxXxilium/linux_dsm_epyc7002.git
synced 2024-12-28 11:18:45 +07:00
721afaa2ae
As always, a large number of DT updates. Too many to enumerate them all,
but at a glance:
New SoCs introduced in this release:
- Amlogic:
+ Meson 8M2 SoC, a.k.a. S812. A quad Cortex-A9 SoC used in some set
top boxes and other products.
- Mediatek:
+ MT7623A, which is a flavor of the MT7623 family with other on-chip
ethernet options.
- Qualcomm:
+ SDM845, a.k.a Snapdragon 845, an 4+4-core Kryo 385/845
(Cortex-A75/A55 derivative) SoC that's one of the current high-end
mobile SoCs.
It's great to see mainline support for it. So far, you
can't do much with it, since a lot of peripherals are not yet in the
DTs but driver support for USB, GPU and other pieces are starting to
trickle in. This might end up being a well-supported SoC upstream if
the momentum keeps up.
- Renesas:
+ R8A77990, a.k.a R-Car E3, a new automotive entertainment-targeted
SoC. Currently only one Cortex-A53 CPU is enabled, we are eagerly
awaiting more. So far, basic drivers such as serial, gpios, PMU and
ethernet are enabled.
+ R8A77470, a.k.a. RZ/G1C, a new dual Cortex-A7 SoC with PowerVR
GPU. Same here, basic set of drivers such as serial, gpios and ethernet
enabled, and SMP support is also forthcoming.
- STMicroelectronics:
+ STM32F469, very similar tih STM32F429 but with display support
Enhancements to SoCs/platforms (DTS contents, some driver portions might
not be in yet):
- Allwinner sun8i (h3/a33/a83t) SMP, DVFS tweaks, misc
- Amlogic Meson: I2C, UFS, TDM, GPIO external interrupts, MMC resets
- Hisilicon hi3660: Thermal cooling, CPU frequency scaling, mailbox interfaces
- Marvell Berlin2CD: SMP support, thermal sensors
- Mediatek MT7623: Highspeed DMA, audio support
- Qualcomm IPQ8074 PCIe support, MSM8996 UFS support
- Renesas: Watchdog and PMU support across many platforms
- Rockchip RK3399: USB3 OTG support
- Samsung Exynos: Audio-over-HDMI on Odroid X/X2/U3
- STMicro STM32: Lots of peripherals added to STM32MP175C
- Uniphier: Ethernet support
New boards:
- Allwinner A20: Olimex A20-SOM-EVB-eMMC variant
- Allwinner H2+: Libre Computer ALL-H3-CC (h2+ version)
- Allwinner A33: Nintendo NES/SuperNES Classic Edition
- Aspeed: S2600WF, Inventec Lanyang BMC, Portwell Neptune
- Berlin2CD: Valve Steam Link
- Broadcom BCM5301X: Luxul XAP-1610 and XWR-3150 V1
- Broadcom: Raspberry Pi 3 B+
- Mediatek MT7623N and MT7623A: reference boards
- Meson 8M2: Tronsmart MXIII Plus
- NXP i.MX: Engicam i.CoreM6, DHCOM iMX6 SOM, BTicino i.MX6DL Mamoj
- Qualcomm MSM8974: Sony Xperia Z1 Compact support
- Qualcomm SDM845: MTP development board
- Renesas: Ebisu R8A77990 board
- Renesas RZ/G1C: iwg23s: iWave G235-SDB
- TI am335x: Pocketbeagle support
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Merge tag 'armsoc-dt' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc
Pull ARM SoC device tree updates from Olof Johansson:
"As always, a large number of DT updates. Too many to enumerate them
all, but at a glance:
New SoCs introduced in this release:
- Amlogic:
+ Meson 8M2 SoC, a.k.a. S812. A quad Cortex-A9 SoC used in some
set top boxes and other products.
- Mediatek:
+ MT7623A, which is a flavor of the MT7623 family with other
on-chip ethernet options.
- Qualcomm:
+ SDM845, a.k.a Snapdragon 845, an 4+4-core Kryo 385/845
(Cortex-A75/A55 derivative) SoC that's one of the current
high-end mobile SoCs.
It's great to see mainline support for it. So far, you can't do
much with it, since a lot of peripherals are not yet in the DTs
but driver support for USB, GPU and other pieces are starting to
trickle in. This might end up being a well-supported SoC
upstream if the momentum keeps up.
- Renesas:
+ R8A77990, a.k.a R-Car E3, a new automotive
entertainment-targeted SoC. Currently only one Cortex-A53 CPU is
enabled, we are eagerly awaiting more. So far, basic drivers
such as serial, gpios, PMU and ethernet are enabled.
+ R8A77470, a.k.a. RZ/G1C, a new dual Cortex-A7 SoC with PowerVR
GPU. Same here, basic set of drivers such as serial, gpios and
ethernet enabled, and SMP support is also forthcoming.
- STMicroelectronics:
+ STM32F469, very similar tih STM32F429 but with display support
Enhancements to SoCs/platforms (DTS contents, some driver portions
might not be in yet):
- Allwinner sun8i (h3/a33/a83t) SMP, DVFS tweaks, misc
- Amlogic Meson: I2C, UFS, TDM, GPIO external interrupts, MMC resets
- Hisilicon hi3660: Thermal cooling, CPU frequency scaling, mailbox interfaces
- Marvell Berlin2CD: SMP support, thermal sensors
- Mediatek MT7623: Highspeed DMA, audio support
- Qualcomm IPQ8074 PCIe support, MSM8996 UFS support
- Renesas: Watchdog and PMU support across many platforms
- Rockchip RK3399: USB3 OTG support
- Samsung Exynos: Audio-over-HDMI on Odroid X/X2/U3
- STMicro STM32: Lots of peripherals added to STM32MP175C
- Uniphier: Ethernet support
New boards:
- Allwinner A20: Olimex A20-SOM-EVB-eMMC variant
- Allwinner H2+: Libre Computer ALL-H3-CC (h2+ version)
- Allwinner A33: Nintendo NES/SuperNES Classic Edition
- Aspeed: S2600WF, Inventec Lanyang BMC, Portwell Neptune
- Berlin2CD: Valve Steam Link
- Broadcom BCM5301X: Luxul XAP-1610 and XWR-3150 V1
- Broadcom: Raspberry Pi 3 B+
- Mediatek MT7623N and MT7623A: reference boards
- Meson 8M2: Tronsmart MXIII Plus
- NXP i.MX: Engicam i.CoreM6, DHCOM iMX6 SOM, BTicino i.MX6DL Mamoj
- Qualcomm MSM8974: Sony Xperia Z1 Compact support
- Qualcomm SDM845: MTP development board
- Renesas: Ebisu R8A77990 board
- Renesas RZ/G1C: iwg23s: iWave G235-SDB
- TI am335x: Pocketbeagle support"
* tag 'armsoc-dt' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc: (448 commits)
ARM: dts: aspeed: Fix hwrng register address
arm64: dts: sprd: whale2: Add the rtc enable clock for watchdog
arm64: dts: sprd: Add GPIO and GPIO keys device nodes
arm64: dts: sprd: fix typo in 'remote-endpoint'
arm64: dts: apq8096-db820c: Removed bt-en-1-8v regulator
arm64: dts: fix regulator property name for wlan pcie endpoint
arm64: dts: qcom: msm8996: Use UFS_GDSC for UFS
ARM: dts: pxa3xx: fix MMC clocks
ARM: pxa: dts: add pin definitions for extended GPIOs
ARM: pxa: dts: add gpio-ranges to gpio controller
ARM: dts: ipq8074: Enable few peripherals for hk01 board
ARM: dts: ipq8074: Add pcie nodes
ARM: dts: ipq8074: Add peripheral nodes
ARM: dts: ipq4019: Add qcom-ipq4019-ap.dk07.1-c2 board file
ARM: dts: ipq4019: Add qcom-ipq4019-ap.dk07.1-c1 board file
ARM: dts: ipq4019: Add ipq4019-ap.dk07.1 common data
ARM: dts: ipq4019: Add qcom-ipq4019-ap.dk04.1-c3 board file
ARM: dts: ipq4019: Add ipq4019-ap.dk04.1-c1 board file
ARM: dts: ipq4019: Add ipq4019-ap.dk04.dtsi
ARM: dts: ipq4019: Change the max opp frequency
...
654 lines
14 KiB
Plaintext
654 lines
14 KiB
Plaintext
// SPDX-License-Identifier: GPL-2.0+ OR MIT
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//
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// Device Tree Source for UniPhier LD20 SoC
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//
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// Copyright (C) 2015-2016 Socionext Inc.
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// Author: Masahiro Yamada <yamada.masahiro@socionext.com>
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#include <dt-bindings/gpio/gpio.h>
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#include <dt-bindings/gpio/uniphier-gpio.h>
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#include <dt-bindings/thermal/thermal.h>
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/memreserve/ 0x80000000 0x02000000;
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/ {
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compatible = "socionext,uniphier-ld20";
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#address-cells = <2>;
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#size-cells = <2>;
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interrupt-parent = <&gic>;
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cpus {
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#address-cells = <2>;
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#size-cells = <0>;
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cpu-map {
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cluster0 {
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core0 {
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cpu = <&cpu0>;
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};
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core1 {
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cpu = <&cpu1>;
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};
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};
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cluster1 {
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core0 {
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cpu = <&cpu2>;
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};
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core1 {
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cpu = <&cpu3>;
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};
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};
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};
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cpu0: cpu@0 {
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device_type = "cpu";
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compatible = "arm,cortex-a72", "arm,armv8";
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reg = <0 0x000>;
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clocks = <&sys_clk 32>;
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enable-method = "psci";
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operating-points-v2 = <&cluster0_opp>;
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#cooling-cells = <2>;
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};
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cpu1: cpu@1 {
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device_type = "cpu";
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compatible = "arm,cortex-a72", "arm,armv8";
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reg = <0 0x001>;
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clocks = <&sys_clk 32>;
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enable-method = "psci";
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operating-points-v2 = <&cluster0_opp>;
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};
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cpu2: cpu@100 {
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device_type = "cpu";
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compatible = "arm,cortex-a53", "arm,armv8";
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reg = <0 0x100>;
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clocks = <&sys_clk 33>;
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enable-method = "psci";
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operating-points-v2 = <&cluster1_opp>;
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#cooling-cells = <2>;
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};
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cpu3: cpu@101 {
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device_type = "cpu";
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compatible = "arm,cortex-a53", "arm,armv8";
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reg = <0 0x101>;
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clocks = <&sys_clk 33>;
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enable-method = "psci";
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operating-points-v2 = <&cluster1_opp>;
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};
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};
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cluster0_opp: opp-table0 {
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compatible = "operating-points-v2";
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opp-shared;
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opp-250000000 {
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opp-hz = /bits/ 64 <250000000>;
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clock-latency-ns = <300>;
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};
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opp-275000000 {
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opp-hz = /bits/ 64 <275000000>;
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clock-latency-ns = <300>;
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};
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opp-500000000 {
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opp-hz = /bits/ 64 <500000000>;
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clock-latency-ns = <300>;
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};
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opp-550000000 {
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opp-hz = /bits/ 64 <550000000>;
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clock-latency-ns = <300>;
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};
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opp-666667000 {
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opp-hz = /bits/ 64 <666667000>;
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clock-latency-ns = <300>;
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};
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opp-733334000 {
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opp-hz = /bits/ 64 <733334000>;
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clock-latency-ns = <300>;
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};
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opp-1000000000 {
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opp-hz = /bits/ 64 <1000000000>;
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clock-latency-ns = <300>;
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};
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opp-1100000000 {
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opp-hz = /bits/ 64 <1100000000>;
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clock-latency-ns = <300>;
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};
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};
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cluster1_opp: opp-table1 {
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compatible = "operating-points-v2";
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opp-shared;
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opp-250000000 {
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opp-hz = /bits/ 64 <250000000>;
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clock-latency-ns = <300>;
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};
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opp-275000000 {
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opp-hz = /bits/ 64 <275000000>;
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clock-latency-ns = <300>;
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};
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opp-500000000 {
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opp-hz = /bits/ 64 <500000000>;
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clock-latency-ns = <300>;
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};
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opp-550000000 {
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opp-hz = /bits/ 64 <550000000>;
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clock-latency-ns = <300>;
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};
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opp-666667000 {
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opp-hz = /bits/ 64 <666667000>;
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clock-latency-ns = <300>;
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};
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opp-733334000 {
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opp-hz = /bits/ 64 <733334000>;
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clock-latency-ns = <300>;
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};
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opp-1000000000 {
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opp-hz = /bits/ 64 <1000000000>;
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clock-latency-ns = <300>;
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};
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opp-1100000000 {
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opp-hz = /bits/ 64 <1100000000>;
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clock-latency-ns = <300>;
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};
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};
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psci {
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compatible = "arm,psci-1.0";
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method = "smc";
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};
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clocks {
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refclk: ref {
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compatible = "fixed-clock";
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#clock-cells = <0>;
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clock-frequency = <25000000>;
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};
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};
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emmc_pwrseq: emmc-pwrseq {
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compatible = "mmc-pwrseq-emmc";
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reset-gpios = <&gpio UNIPHIER_GPIO_PORT(3, 2) GPIO_ACTIVE_LOW>;
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};
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timer {
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compatible = "arm,armv8-timer";
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interrupts = <1 13 4>,
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<1 14 4>,
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<1 11 4>,
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<1 10 4>;
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};
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thermal-zones {
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cpu-thermal {
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polling-delay-passive = <250>; /* 250ms */
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polling-delay = <1000>; /* 1000ms */
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thermal-sensors = <&pvtctl>;
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trips {
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cpu_crit: cpu-crit {
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temperature = <110000>; /* 110C */
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hysteresis = <2000>;
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type = "critical";
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};
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cpu_alert: cpu-alert {
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temperature = <100000>; /* 100C */
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hysteresis = <2000>;
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type = "passive";
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};
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};
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cooling-maps {
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map0 {
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trip = <&cpu_alert>;
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cooling-device = <&cpu0
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THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
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};
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map1 {
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trip = <&cpu_alert>;
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cooling-device = <&cpu2
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THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
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};
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};
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};
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};
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soc@0 {
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compatible = "simple-bus";
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#address-cells = <1>;
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#size-cells = <1>;
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ranges = <0 0 0 0xffffffff>;
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serial0: serial@54006800 {
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compatible = "socionext,uniphier-uart";
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status = "disabled";
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reg = <0x54006800 0x40>;
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interrupts = <0 33 4>;
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_uart0>;
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clocks = <&peri_clk 0>;
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resets = <&peri_rst 0>;
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};
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serial1: serial@54006900 {
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compatible = "socionext,uniphier-uart";
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status = "disabled";
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reg = <0x54006900 0x40>;
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interrupts = <0 35 4>;
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_uart1>;
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clocks = <&peri_clk 1>;
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resets = <&peri_rst 1>;
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};
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serial2: serial@54006a00 {
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compatible = "socionext,uniphier-uart";
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status = "disabled";
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reg = <0x54006a00 0x40>;
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interrupts = <0 37 4>;
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_uart2>;
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clocks = <&peri_clk 2>;
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resets = <&peri_rst 2>;
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};
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serial3: serial@54006b00 {
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compatible = "socionext,uniphier-uart";
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status = "disabled";
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reg = <0x54006b00 0x40>;
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interrupts = <0 177 4>;
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_uart3>;
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clocks = <&peri_clk 3>;
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resets = <&peri_rst 3>;
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};
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gpio: gpio@55000000 {
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compatible = "socionext,uniphier-gpio";
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reg = <0x55000000 0x200>;
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interrupt-parent = <&aidet>;
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interrupt-controller;
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#interrupt-cells = <2>;
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gpio-controller;
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#gpio-cells = <2>;
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gpio-ranges = <&pinctrl 0 0 0>,
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<&pinctrl 96 0 0>,
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<&pinctrl 160 0 0>;
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gpio-ranges-group-names = "gpio_range0",
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"gpio_range1",
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"gpio_range2";
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ngpios = <205>;
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socionext,interrupt-ranges = <0 48 16>, <16 154 5>,
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<21 217 3>;
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};
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audio@56000000 {
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compatible = "socionext,uniphier-ld20-aio";
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reg = <0x56000000 0x80000>;
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interrupts = <0 144 4>;
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_aout1>,
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<&pinctrl_aoutiec1>;
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clock-names = "aio";
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clocks = <&sys_clk 40>;
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reset-names = "aio";
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resets = <&sys_rst 40>;
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#sound-dai-cells = <1>;
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socionext,syscon = <&soc_glue>;
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i2s_port0: port@0 {
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i2s_hdmi: endpoint {
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};
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};
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i2s_port1: port@1 {
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i2s_pcmin2: endpoint {
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};
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};
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i2s_port2: port@2 {
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i2s_line: endpoint {
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dai-format = "i2s";
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remote-endpoint = <&evea_line>;
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};
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};
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i2s_port3: port@3 {
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i2s_hpcmout1: endpoint {
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};
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};
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i2s_port4: port@4 {
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i2s_hp: endpoint {
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dai-format = "i2s";
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remote-endpoint = <&evea_hp>;
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};
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};
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spdif_port0: port@5 {
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spdif_hiecout1: endpoint {
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};
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};
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src_port0: port@6 {
|
|
i2s_epcmout2: endpoint {
|
|
};
|
|
};
|
|
|
|
src_port1: port@7 {
|
|
i2s_epcmout3: endpoint {
|
|
};
|
|
};
|
|
|
|
comp_spdif_port0: port@8 {
|
|
comp_spdif_hiecout1: endpoint {
|
|
};
|
|
};
|
|
};
|
|
|
|
codec@57900000 {
|
|
compatible = "socionext,uniphier-evea";
|
|
reg = <0x57900000 0x1000>;
|
|
clock-names = "evea", "exiv";
|
|
clocks = <&sys_clk 41>, <&sys_clk 42>;
|
|
reset-names = "evea", "exiv", "adamv";
|
|
resets = <&sys_rst 41>, <&sys_rst 42>, <&adamv_rst 0>;
|
|
#sound-dai-cells = <1>;
|
|
|
|
port@0 {
|
|
evea_line: endpoint {
|
|
remote-endpoint = <&i2s_line>;
|
|
};
|
|
};
|
|
|
|
port@1 {
|
|
evea_hp: endpoint {
|
|
remote-endpoint = <&i2s_hp>;
|
|
};
|
|
};
|
|
};
|
|
|
|
adamv@57920000 {
|
|
compatible = "socionext,uniphier-ld20-adamv",
|
|
"simple-mfd", "syscon";
|
|
reg = <0x57920000 0x1000>;
|
|
|
|
adamv_rst: reset {
|
|
compatible = "socionext,uniphier-ld20-adamv-reset";
|
|
#reset-cells = <1>;
|
|
};
|
|
};
|
|
|
|
i2c0: i2c@58780000 {
|
|
compatible = "socionext,uniphier-fi2c";
|
|
status = "disabled";
|
|
reg = <0x58780000 0x80>;
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
interrupts = <0 41 4>;
|
|
pinctrl-names = "default";
|
|
pinctrl-0 = <&pinctrl_i2c0>;
|
|
clocks = <&peri_clk 4>;
|
|
resets = <&peri_rst 4>;
|
|
clock-frequency = <100000>;
|
|
};
|
|
|
|
i2c1: i2c@58781000 {
|
|
compatible = "socionext,uniphier-fi2c";
|
|
status = "disabled";
|
|
reg = <0x58781000 0x80>;
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
interrupts = <0 42 4>;
|
|
pinctrl-names = "default";
|
|
pinctrl-0 = <&pinctrl_i2c1>;
|
|
clocks = <&peri_clk 5>;
|
|
resets = <&peri_rst 5>;
|
|
clock-frequency = <100000>;
|
|
};
|
|
|
|
i2c2: i2c@58782000 {
|
|
compatible = "socionext,uniphier-fi2c";
|
|
reg = <0x58782000 0x80>;
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
interrupts = <0 43 4>;
|
|
clocks = <&peri_clk 6>;
|
|
resets = <&peri_rst 6>;
|
|
clock-frequency = <400000>;
|
|
};
|
|
|
|
i2c3: i2c@58783000 {
|
|
compatible = "socionext,uniphier-fi2c";
|
|
status = "disabled";
|
|
reg = <0x58783000 0x80>;
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
interrupts = <0 44 4>;
|
|
pinctrl-names = "default";
|
|
pinctrl-0 = <&pinctrl_i2c3>;
|
|
clocks = <&peri_clk 7>;
|
|
resets = <&peri_rst 7>;
|
|
clock-frequency = <100000>;
|
|
};
|
|
|
|
i2c4: i2c@58784000 {
|
|
compatible = "socionext,uniphier-fi2c";
|
|
status = "disabled";
|
|
reg = <0x58784000 0x80>;
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
interrupts = <0 45 4>;
|
|
pinctrl-names = "default";
|
|
pinctrl-0 = <&pinctrl_i2c4>;
|
|
clocks = <&peri_clk 8>;
|
|
resets = <&peri_rst 8>;
|
|
clock-frequency = <100000>;
|
|
};
|
|
|
|
i2c5: i2c@58785000 {
|
|
compatible = "socionext,uniphier-fi2c";
|
|
reg = <0x58785000 0x80>;
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
interrupts = <0 25 4>;
|
|
clocks = <&peri_clk 9>;
|
|
resets = <&peri_rst 9>;
|
|
clock-frequency = <400000>;
|
|
};
|
|
|
|
system_bus: system-bus@58c00000 {
|
|
compatible = "socionext,uniphier-system-bus";
|
|
status = "disabled";
|
|
reg = <0x58c00000 0x400>;
|
|
#address-cells = <2>;
|
|
#size-cells = <1>;
|
|
pinctrl-names = "default";
|
|
pinctrl-0 = <&pinctrl_system_bus>;
|
|
};
|
|
|
|
smpctrl@59801000 {
|
|
compatible = "socionext,uniphier-smpctrl";
|
|
reg = <0x59801000 0x400>;
|
|
};
|
|
|
|
sdctrl@59810000 {
|
|
compatible = "socionext,uniphier-ld20-sdctrl",
|
|
"simple-mfd", "syscon";
|
|
reg = <0x59810000 0x400>;
|
|
|
|
sd_clk: clock {
|
|
compatible = "socionext,uniphier-ld20-sd-clock";
|
|
#clock-cells = <1>;
|
|
};
|
|
|
|
sd_rst: reset {
|
|
compatible = "socionext,uniphier-ld20-sd-reset";
|
|
#reset-cells = <1>;
|
|
};
|
|
};
|
|
|
|
perictrl@59820000 {
|
|
compatible = "socionext,uniphier-ld20-perictrl",
|
|
"simple-mfd", "syscon";
|
|
reg = <0x59820000 0x200>;
|
|
|
|
peri_clk: clock {
|
|
compatible = "socionext,uniphier-ld20-peri-clock";
|
|
#clock-cells = <1>;
|
|
};
|
|
|
|
peri_rst: reset {
|
|
compatible = "socionext,uniphier-ld20-peri-reset";
|
|
#reset-cells = <1>;
|
|
};
|
|
};
|
|
|
|
emmc: sdhc@5a000000 {
|
|
compatible = "socionext,uniphier-sd4hc", "cdns,sd4hc";
|
|
reg = <0x5a000000 0x400>;
|
|
interrupts = <0 78 4>;
|
|
pinctrl-names = "default";
|
|
pinctrl-0 = <&pinctrl_emmc>;
|
|
clocks = <&sys_clk 4>;
|
|
resets = <&sys_rst 4>;
|
|
bus-width = <8>;
|
|
mmc-ddr-1_8v;
|
|
mmc-hs200-1_8v;
|
|
mmc-pwrseq = <&emmc_pwrseq>;
|
|
cdns,phy-input-delay-legacy = <9>;
|
|
cdns,phy-input-delay-mmc-highspeed = <2>;
|
|
cdns,phy-input-delay-mmc-ddr = <3>;
|
|
cdns,phy-dll-delay-sdclk = <21>;
|
|
cdns,phy-dll-delay-sdclk-hsmmc = <21>;
|
|
};
|
|
|
|
soc_glue: soc-glue@5f800000 {
|
|
compatible = "socionext,uniphier-ld20-soc-glue",
|
|
"simple-mfd", "syscon";
|
|
reg = <0x5f800000 0x2000>;
|
|
|
|
pinctrl: pinctrl {
|
|
compatible = "socionext,uniphier-ld20-pinctrl";
|
|
};
|
|
};
|
|
|
|
soc-glue@5f900000 {
|
|
compatible = "socionext,uniphier-ld20-soc-glue-debug",
|
|
"simple-mfd";
|
|
#address-cells = <1>;
|
|
#size-cells = <1>;
|
|
ranges = <0 0x5f900000 0x2000>;
|
|
|
|
efuse@100 {
|
|
compatible = "socionext,uniphier-efuse";
|
|
reg = <0x100 0x28>;
|
|
};
|
|
|
|
efuse@200 {
|
|
compatible = "socionext,uniphier-efuse";
|
|
reg = <0x200 0x68>;
|
|
};
|
|
};
|
|
|
|
aidet: aidet@5fc20000 {
|
|
compatible = "socionext,uniphier-ld20-aidet";
|
|
reg = <0x5fc20000 0x200>;
|
|
interrupt-controller;
|
|
#interrupt-cells = <2>;
|
|
};
|
|
|
|
gic: interrupt-controller@5fe00000 {
|
|
compatible = "arm,gic-v3";
|
|
reg = <0x5fe00000 0x10000>, /* GICD */
|
|
<0x5fe80000 0x80000>; /* GICR */
|
|
interrupt-controller;
|
|
#interrupt-cells = <3>;
|
|
interrupts = <1 9 4>;
|
|
};
|
|
|
|
sysctrl@61840000 {
|
|
compatible = "socionext,uniphier-ld20-sysctrl",
|
|
"simple-mfd", "syscon";
|
|
reg = <0x61840000 0x10000>;
|
|
|
|
sys_clk: clock {
|
|
compatible = "socionext,uniphier-ld20-clock";
|
|
#clock-cells = <1>;
|
|
};
|
|
|
|
sys_rst: reset {
|
|
compatible = "socionext,uniphier-ld20-reset";
|
|
#reset-cells = <1>;
|
|
};
|
|
|
|
watchdog {
|
|
compatible = "socionext,uniphier-wdt";
|
|
};
|
|
|
|
pvtctl: pvtctl {
|
|
compatible = "socionext,uniphier-ld20-thermal";
|
|
interrupts = <0 3 4>;
|
|
#thermal-sensor-cells = <0>;
|
|
socionext,tmod-calibration = <0x0f22 0x68ee>;
|
|
};
|
|
};
|
|
|
|
eth: ethernet@65000000 {
|
|
compatible = "socionext,uniphier-ld20-ave4";
|
|
status = "disabled";
|
|
reg = <0x65000000 0x8500>;
|
|
interrupts = <0 66 4>;
|
|
pinctrl-names = "default";
|
|
pinctrl-0 = <&pinctrl_ether_rgmii>;
|
|
clock-names = "ether";
|
|
clocks = <&sys_clk 6>;
|
|
reset-names = "ether";
|
|
resets = <&sys_rst 6>;
|
|
phy-mode = "rgmii";
|
|
local-mac-address = [00 00 00 00 00 00];
|
|
socionext,syscon-phy-mode = <&soc_glue 0>;
|
|
|
|
mdio: mdio {
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
};
|
|
};
|
|
|
|
nand: nand@68000000 {
|
|
compatible = "socionext,uniphier-denali-nand-v5b";
|
|
status = "disabled";
|
|
reg-names = "nand_data", "denali_reg";
|
|
reg = <0x68000000 0x20>, <0x68100000 0x1000>;
|
|
interrupts = <0 65 4>;
|
|
pinctrl-names = "default";
|
|
pinctrl-0 = <&pinctrl_nand>;
|
|
clocks = <&sys_clk 2>;
|
|
resets = <&sys_rst 2>;
|
|
};
|
|
};
|
|
};
|
|
|
|
#include "uniphier-pinctrl.dtsi"
|
|
|
|
&pinctrl_aout1 {
|
|
drive-strength = <4>; /* default: 3.5mA */
|
|
|
|
ao1dacck {
|
|
pins = "AO1DACCK";
|
|
drive-strength = <5>; /* 5mA */
|
|
};
|
|
};
|
|
|
|
&pinctrl_aoutiec1 {
|
|
drive-strength = <4>; /* default: 3.5mA */
|
|
|
|
ao1arc {
|
|
pins = "AO1ARC";
|
|
drive-strength = <11>; /* 11mA */
|
|
};
|
|
};
|