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https://github.com/AuxXxilium/linux_dsm_epyc7002.git
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50579d3d95
Updated copyrights comments and also changed some other comments alignments. Signed-off-by: Raghu Vatsavayi <raghu.vatsavayi@caviumnetworks.com> Signed-off-by: Derek Chickles <derek.chickles@caviumnetworks.com> Signed-off-by: Satanand Burla <satananda.burla@caviumnetworks.com> Signed-off-by: Felix Manlunas <felix.manlunas@caviumnetworks.com> Signed-off-by: David S. Miller <davem@davemloft.net>
46 lines
1.7 KiB
C
46 lines
1.7 KiB
C
/**********************************************************************
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* Author: Cavium, Inc.
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*
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* Contact: support@cavium.com
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* Please include "LiquidIO" in the subject.
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*
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* Copyright (c) 2003-2016 Cavium, Inc.
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*
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* This file is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License, Version 2, as
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* published by the Free Software Foundation.
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*
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* This file is distributed in the hope that it will be useful, but
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* AS-IS and WITHOUT ANY WARRANTY; without even the implied warranty
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* of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE, TITLE, or
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* NONINFRINGEMENT. See the GNU General Public License for more details.
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***********************************************************************/
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/*! \file cn68xx_regs.h
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* \brief Host Driver: Register Address and Register Mask values for
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* Octeon CN68XX devices. The register map for CN66XX is the same
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* for most registers. This file has the other registers that are
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* 68XX-specific.
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*/
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#ifndef __CN68XX_REGS_H__
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#define __CN68XX_REGS_H__
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/*###################### REQUEST QUEUE #########################*/
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#define CN68XX_SLI_IQ_PORT0_PKIND 0x0800
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#define CN68XX_SLI_IQ_PORT_PKIND(iq) \
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(CN68XX_SLI_IQ_PORT0_PKIND + ((iq) * CN6XXX_IQ_OFFSET))
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/*############################ OUTPUT QUEUE #########################*/
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/* Starting pipe number and number of pipes used by the SLI packet output. */
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#define CN68XX_SLI_TX_PIPE 0x1230
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/*######################## INTERRUPTS #########################*/
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/*------------------ Interrupt Masks ----------------*/
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#define CN68XX_INTR_PIPE_ERR BIT_ULL(61)
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#endif
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