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https://github.com/AuxXxilium/linux_dsm_epyc7002.git
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df2a4d94f1
Warn user if clock is used by more than allowed devices. This check is done by firmware and returns respective error code. Upon receiving error code for excessive user, warn user for the same. This change is done to restrict VPLL use count. It is assumed that VPLL is used by one user only. Signed-off-by: Michal Simek <michal.simek@xilinx.com> Signed-off-by: Rajan Vaja <rajan.vaja@xilinx.com> Link: https://lkml.kernel.org/r/1575527759-26452-4-git-send-email-rajan.vaja@xilinx.com Acked-by: Michal Simek <michal.simek@xilinx.com> Signed-off-by: Stephen Boyd <sboyd@kernel.org>
338 lines
8.6 KiB
C
338 lines
8.6 KiB
C
// SPDX-License-Identifier: GPL-2.0
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/*
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* Zynq UltraScale+ MPSoC PLL driver
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*
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* Copyright (C) 2016-2018 Xilinx
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*/
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#include <linux/clk.h>
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#include <linux/clk-provider.h>
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#include <linux/slab.h>
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#include "clk-zynqmp.h"
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/**
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* struct zynqmp_pll - PLL clock
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* @hw: Handle between common and hardware-specific interfaces
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* @clk_id: PLL clock ID
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*/
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struct zynqmp_pll {
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struct clk_hw hw;
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u32 clk_id;
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};
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#define to_zynqmp_pll(_hw) container_of(_hw, struct zynqmp_pll, hw)
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#define PLL_FBDIV_MIN 25
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#define PLL_FBDIV_MAX 125
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#define PS_PLL_VCO_MIN 1500000000
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#define PS_PLL_VCO_MAX 3000000000UL
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enum pll_mode {
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PLL_MODE_INT,
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PLL_MODE_FRAC,
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};
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#define FRAC_OFFSET 0x8
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#define PLLFCFG_FRAC_EN BIT(31)
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#define FRAC_DIV BIT(16) /* 2^16 */
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/**
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* zynqmp_pll_get_mode() - Get mode of PLL
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* @hw: Handle between common and hardware-specific interfaces
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*
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* Return: Mode of PLL
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*/
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static inline enum pll_mode zynqmp_pll_get_mode(struct clk_hw *hw)
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{
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struct zynqmp_pll *clk = to_zynqmp_pll(hw);
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u32 clk_id = clk->clk_id;
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const char *clk_name = clk_hw_get_name(hw);
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u32 ret_payload[PAYLOAD_ARG_CNT];
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int ret;
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const struct zynqmp_eemi_ops *eemi_ops = zynqmp_pm_get_eemi_ops();
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ret = eemi_ops->ioctl(0, IOCTL_GET_PLL_FRAC_MODE, clk_id, 0,
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ret_payload);
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if (ret)
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pr_warn_once("%s() PLL get frac mode failed for %s, ret = %d\n",
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__func__, clk_name, ret);
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return ret_payload[1];
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}
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/**
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* zynqmp_pll_set_mode() - Set the PLL mode
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* @hw: Handle between common and hardware-specific interfaces
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* @on: Flag to determine the mode
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*/
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static inline void zynqmp_pll_set_mode(struct clk_hw *hw, bool on)
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{
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struct zynqmp_pll *clk = to_zynqmp_pll(hw);
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u32 clk_id = clk->clk_id;
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const char *clk_name = clk_hw_get_name(hw);
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int ret;
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u32 mode;
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const struct zynqmp_eemi_ops *eemi_ops = zynqmp_pm_get_eemi_ops();
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if (on)
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mode = PLL_MODE_FRAC;
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else
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mode = PLL_MODE_INT;
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ret = eemi_ops->ioctl(0, IOCTL_SET_PLL_FRAC_MODE, clk_id, mode, NULL);
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if (ret)
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pr_warn_once("%s() PLL set frac mode failed for %s, ret = %d\n",
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__func__, clk_name, ret);
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}
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/**
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* zynqmp_pll_round_rate() - Round a clock frequency
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* @hw: Handle between common and hardware-specific interfaces
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* @rate: Desired clock frequency
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* @prate: Clock frequency of parent clock
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*
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* Return: Frequency closest to @rate the hardware can generate
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*/
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static long zynqmp_pll_round_rate(struct clk_hw *hw, unsigned long rate,
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unsigned long *prate)
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{
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u32 fbdiv;
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long rate_div, f;
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/* Enable the fractional mode if needed */
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rate_div = (rate * FRAC_DIV) / *prate;
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f = rate_div % FRAC_DIV;
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zynqmp_pll_set_mode(hw, !!f);
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if (zynqmp_pll_get_mode(hw) == PLL_MODE_FRAC) {
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if (rate > PS_PLL_VCO_MAX) {
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fbdiv = rate / PS_PLL_VCO_MAX;
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rate = rate / (fbdiv + 1);
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}
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if (rate < PS_PLL_VCO_MIN) {
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fbdiv = DIV_ROUND_UP(PS_PLL_VCO_MIN, rate);
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rate = rate * fbdiv;
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}
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return rate;
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}
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fbdiv = DIV_ROUND_CLOSEST(rate, *prate);
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fbdiv = clamp_t(u32, fbdiv, PLL_FBDIV_MIN, PLL_FBDIV_MAX);
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return *prate * fbdiv;
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}
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/**
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* zynqmp_pll_recalc_rate() - Recalculate clock frequency
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* @hw: Handle between common and hardware-specific interfaces
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* @parent_rate: Clock frequency of parent clock
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*
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* Return: Current clock frequency
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*/
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static unsigned long zynqmp_pll_recalc_rate(struct clk_hw *hw,
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unsigned long parent_rate)
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{
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struct zynqmp_pll *clk = to_zynqmp_pll(hw);
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u32 clk_id = clk->clk_id;
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const char *clk_name = clk_hw_get_name(hw);
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u32 fbdiv, data;
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unsigned long rate, frac;
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u32 ret_payload[PAYLOAD_ARG_CNT];
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int ret;
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const struct zynqmp_eemi_ops *eemi_ops = zynqmp_pm_get_eemi_ops();
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ret = eemi_ops->clock_getdivider(clk_id, &fbdiv);
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if (ret)
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pr_warn_once("%s() get divider failed for %s, ret = %d\n",
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__func__, clk_name, ret);
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rate = parent_rate * fbdiv;
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if (zynqmp_pll_get_mode(hw) == PLL_MODE_FRAC) {
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eemi_ops->ioctl(0, IOCTL_GET_PLL_FRAC_DATA, clk_id, 0,
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ret_payload);
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data = ret_payload[1];
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frac = (parent_rate * data) / FRAC_DIV;
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rate = rate + frac;
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}
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return rate;
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}
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/**
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* zynqmp_pll_set_rate() - Set rate of PLL
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* @hw: Handle between common and hardware-specific interfaces
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* @rate: Frequency of clock to be set
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* @parent_rate: Clock frequency of parent clock
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*
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* Set PLL divider to set desired rate.
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*
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* Returns: rate which is set on success else error code
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*/
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static int zynqmp_pll_set_rate(struct clk_hw *hw, unsigned long rate,
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unsigned long parent_rate)
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{
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struct zynqmp_pll *clk = to_zynqmp_pll(hw);
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u32 clk_id = clk->clk_id;
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const char *clk_name = clk_hw_get_name(hw);
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u32 fbdiv;
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long rate_div, frac, m, f;
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int ret;
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const struct zynqmp_eemi_ops *eemi_ops = zynqmp_pm_get_eemi_ops();
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if (zynqmp_pll_get_mode(hw) == PLL_MODE_FRAC) {
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rate_div = (rate * FRAC_DIV) / parent_rate;
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m = rate_div / FRAC_DIV;
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f = rate_div % FRAC_DIV;
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m = clamp_t(u32, m, (PLL_FBDIV_MIN), (PLL_FBDIV_MAX));
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rate = parent_rate * m;
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frac = (parent_rate * f) / FRAC_DIV;
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ret = eemi_ops->clock_setdivider(clk_id, m);
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if (ret == -EUSERS)
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WARN(1, "More than allowed devices are using the %s, which is forbidden\n",
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clk_name);
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else if (ret)
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pr_warn_once("%s() set divider failed for %s, ret = %d\n",
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__func__, clk_name, ret);
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eemi_ops->ioctl(0, IOCTL_SET_PLL_FRAC_DATA, clk_id, f, NULL);
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return rate + frac;
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}
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fbdiv = DIV_ROUND_CLOSEST(rate, parent_rate);
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fbdiv = clamp_t(u32, fbdiv, PLL_FBDIV_MIN, PLL_FBDIV_MAX);
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ret = eemi_ops->clock_setdivider(clk_id, fbdiv);
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if (ret)
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pr_warn_once("%s() set divider failed for %s, ret = %d\n",
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__func__, clk_name, ret);
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return parent_rate * fbdiv;
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}
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/**
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* zynqmp_pll_is_enabled() - Check if a clock is enabled
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* @hw: Handle between common and hardware-specific interfaces
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*
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* Return: 1 if the clock is enabled, 0 otherwise
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*/
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static int zynqmp_pll_is_enabled(struct clk_hw *hw)
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{
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struct zynqmp_pll *clk = to_zynqmp_pll(hw);
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const char *clk_name = clk_hw_get_name(hw);
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u32 clk_id = clk->clk_id;
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unsigned int state;
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int ret;
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const struct zynqmp_eemi_ops *eemi_ops = zynqmp_pm_get_eemi_ops();
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ret = eemi_ops->clock_getstate(clk_id, &state);
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if (ret) {
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pr_warn_once("%s() clock get state failed for %s, ret = %d\n",
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__func__, clk_name, ret);
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return -EIO;
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}
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return state ? 1 : 0;
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}
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/**
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* zynqmp_pll_enable() - Enable clock
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* @hw: Handle between common and hardware-specific interfaces
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*
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* Return: 0 on success else error code
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*/
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static int zynqmp_pll_enable(struct clk_hw *hw)
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{
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struct zynqmp_pll *clk = to_zynqmp_pll(hw);
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const char *clk_name = clk_hw_get_name(hw);
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u32 clk_id = clk->clk_id;
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int ret;
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const struct zynqmp_eemi_ops *eemi_ops = zynqmp_pm_get_eemi_ops();
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if (zynqmp_pll_is_enabled(hw))
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return 0;
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ret = eemi_ops->clock_enable(clk_id);
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if (ret)
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pr_warn_once("%s() clock enable failed for %s, ret = %d\n",
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__func__, clk_name, ret);
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return ret;
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}
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/**
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* zynqmp_pll_disable() - Disable clock
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* @hw: Handle between common and hardware-specific interfaces
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*/
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static void zynqmp_pll_disable(struct clk_hw *hw)
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{
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struct zynqmp_pll *clk = to_zynqmp_pll(hw);
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const char *clk_name = clk_hw_get_name(hw);
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u32 clk_id = clk->clk_id;
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int ret;
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const struct zynqmp_eemi_ops *eemi_ops = zynqmp_pm_get_eemi_ops();
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if (!zynqmp_pll_is_enabled(hw))
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return;
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ret = eemi_ops->clock_disable(clk_id);
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if (ret)
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pr_warn_once("%s() clock disable failed for %s, ret = %d\n",
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__func__, clk_name, ret);
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}
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static const struct clk_ops zynqmp_pll_ops = {
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.enable = zynqmp_pll_enable,
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.disable = zynqmp_pll_disable,
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.is_enabled = zynqmp_pll_is_enabled,
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.round_rate = zynqmp_pll_round_rate,
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.recalc_rate = zynqmp_pll_recalc_rate,
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.set_rate = zynqmp_pll_set_rate,
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};
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/**
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* zynqmp_clk_register_pll() - Register PLL with the clock framework
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* @name: PLL name
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* @clk_id: Clock ID
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* @parents: Name of this clock's parents
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* @num_parents: Number of parents
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* @nodes: Clock topology node
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*
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* Return: clock hardware to the registered clock
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*/
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struct clk_hw *zynqmp_clk_register_pll(const char *name, u32 clk_id,
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const char * const *parents,
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u8 num_parents,
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const struct clock_topology *nodes)
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{
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struct zynqmp_pll *pll;
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struct clk_hw *hw;
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struct clk_init_data init;
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int ret;
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init.name = name;
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init.ops = &zynqmp_pll_ops;
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init.flags = nodes->flag;
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init.parent_names = parents;
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init.num_parents = 1;
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pll = kzalloc(sizeof(*pll), GFP_KERNEL);
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if (!pll)
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return ERR_PTR(-ENOMEM);
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pll->hw.init = &init;
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pll->clk_id = clk_id;
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hw = &pll->hw;
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ret = clk_hw_register(NULL, hw);
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if (ret) {
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kfree(pll);
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return ERR_PTR(ret);
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}
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clk_hw_set_rate_range(hw, PS_PLL_VCO_MIN, PS_PLL_VCO_MAX);
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if (ret < 0)
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pr_err("%s:ERROR clk_set_rate_range failed %d\n", name, ret);
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return hw;
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}
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