mirror of
https://github.com/AuxXxilium/linux_dsm_epyc7002.git
synced 2024-12-27 15:05:03 +07:00
7318413077
Pull MIPS updates from Ralf Baechle:
"This is the main pull request for 4.14 for MIPS; below a summary of
the non-merge commits:
CM:
- Rename mips_cm_base to mips_gcr_base
- Specify register size when generating accessors
- Use BIT/GENMASK for register fields, order & drop shifts
- Add cluster & block args to mips_cm_lock_other()
CPC:
- Use common CPS accessor generation macros
- Use BIT/GENMASK for register fields, order & drop shifts
- Introduce register modify (set/clear/change) accessors
- Use change_*, set_* & clear_* where appropriate
- Add CM/CPC 3.5 register definitions
- Use GlobalNumber macros rather than magic numbers
- Have asm/mips-cps.h include CM & CPC headers
- Cluster support for topology functions
- Detect CPUs in secondary clusters
CPS:
- Read GIC_VL_IDENT directly, not via irqchip driver
DMA:
- Consolidate coherent and non-coherent dma_alloc code
- Don't use dma_cache_sync to implement fd_cacheflush
FPU emulation / FP assist code:
- Another series of 14 commits fixing corner cases such as NaN
propgagation and other special input values.
- Zero bits 32-63 of the result for a CLASS.D instruction.
- Enhanced statics via debugfs
- Do not use bools for arithmetic. GCC 7.1 moans about this.
- Correct user fault_addr type
Generic MIPS:
- Enhancement of stack backtraces
- Cleanup from non-existing options
- Handle non word sized instructions when examining frame
- Fix detection and decoding of ADDIUSP instruction
- Fix decoding of SWSP16 instruction
- Refactor handling of stack pointer in get_frame_info
- Remove unreachable code from force_fcr31_sig()
- Convert to using %pOF instead of full_name
- Remove the R6000 support.
- Move FP code from *_switch.S to *_fpu.S
- Remove unused ST_OFF from r2300_switch.S
- Allow platform to specify multiple its.S files
- Add #includes to various files to ensure code builds reliable and
without warning..
- Remove __invalidate_kernel_vmap_range
- Remove plat_timer_setup
- Declare various variables & functions static
- Abstract CPU core & VP(E) ID access through accessor functions
- Store core & VP IDs in GlobalNumber-style variable
- Unify checks for sibling CPUs
- Add CPU cluster number accessors
- Prevent direct use of generic_defconfig
- Make CONFIG_MIPS_MT_SMP default y
- Add __ioread64_copy
- Remove unnecessary inclusions of linux/irqchip/mips-gic.h
GIC:
- Introduce asm/mips-gic.h with accessor functions
- Use new GIC accessor functions in mips-gic-timer
- Remove counter access functions from irq-mips-gic.c
- Remove gic_read_local_vp_id() from irq-mips-gic.c
- Simplify shared interrupt pending/mask reads in irq-mips-gic.c
- Simplify gic_local_irq_domain_map() in irq-mips-gic.c
- Drop gic_(re)set_mask() functions in irq-mips-gic.c
- Remove gic_set_polarity(), gic_set_trigger(), gic_set_dual_edge(),
gic_map_to_pin() and gic_map_to_vpe() from irq-mips-gic.c.
- Convert remaining shared reg access, local int mask access and
remaining local reg access to new accessors
- Move GIC_LOCAL_INT_* to asm/mips-gic.h
- Remove GIC_CPU_INT* macros from irq-mips-gic.c
- Move various definitions to the driver
- Remove gic_get_usm_range()
- Remove __gic_irq_dispatch() forward declaration
- Remove gic_init()
- Use mips_gic_present() in place of gic_present and remove
gic_present
- Move gic_get_c0_*_int() to asm/mips-gic.h
- Remove linux/irqchip/mips-gic.h
- Inline __gic_init()
- Inline gic_basic_init()
- Make pcpu_masks a per-cpu variable
- Use pcpu_masks to avoid reading GIC_SH_MASK*
- Clean up mti, reserved-cpu-vectors handling
- Use cpumask_first_and() in gic_set_affinity()
- Let the core set struct irq_common_data affinity
microMIPS:
- Fix microMIPS stack unwinding on big endian systems
MIPS-GIC:
- SYNC after enabling GIC region
NUMA:
- Remove the unused parent_node() macro
R6:
- Constify r2_decoder_tables
- Add accessor & bit definitions for GlobalNumber
SMP:
- Constify smp ops
- Allow boot_secondary SMP op to return errors
VDSO:
- Drop gic_get_usm_range() usage
- Avoid use of linux/irqchip/mips-gic.h
Platform changes:
Alchemy:
- Add devboard machine type to cpuinfo
- update cpu feature overrides
- Threaded carddetect irqs for devboards
AR7:
- allow NULL clock for clk_get_rate
BCM63xx:
- Fix ENETDMA_6345_MAXBURST_REG offset
- Allow NULL clock for clk_get_rate
CI20:
- Enable GPIO and RTC drivers in defconfig
- Add ethernet and fixed-regulator nodes to DTS
Generic platform:
- Move Boston and NI 169445 FIT image source to their own files
- Include asm/bootinfo.h for plat_fdt_relocated()
- Include asm/time.h for get_c0_*_int()
- Include asm/bootinfo.h for plat_fdt_relocated()
- Include asm/time.h for get_c0_*_int()
- Allow filtering enabled boards by requirements
- Don't explicitly disable CONFIG_USB_SUPPORT
- Bump default NR_CPUS to 16
JZ4700:
- Probe the jz4740-rtc driver from devicetree
Lantiq:
- Drop check of boot select from the spi-falcon driver.
- Drop check of boot select from the lantiq-flash MTD driver.
- Access boot cause register in the watchdog driver through regmap
- Add device tree binding documentation for the watchdog driver
- Add docs for the RCU DT bindings.
- Convert the fpi bus driver to a platform_driver
- Remove ltq_reset_cause() and ltq_boot_select(
- Switch to a proper reset driver
- Switch to a new drivers/soc GPHY driver
- Add an USB PHY driver for the Lantiq SoCs using the RCU module
- Use of_platform_default_populate instead of __dt_register_buses
- Enable MFD_SYSCON to be able to use it for the RCU MFD
- Replace ltq_boot_select() with dummy implementation.
Loongson 2F:
- Allow NULL clock for clk_get_rate
Malta:
- Use new GIC accessor functions
NI 169445:
- Add support for NI 169445 board.
- Only include in 32r2el kernels
Octeon:
- Add support for watchdog of 78XX SOCs.
- Add support for watchdog of CN68XX SOCs.
- Expose support for mips32r1, mips32r2 and mips64r1
- Enable more drivers in config file
- Add support for accessing the boot vector.
- Remove old boot vector code from watchdog driver
- Define watchdog registers for 70xx, 73xx, 78xx, F75xx.
- Make CSR functions node aware.
- Allow access to CIU3 IRQ domains.
- Misc cleanups in the watchdog driver
Omega2+:
- New board, add support and defconfig
Pistachio:
- Enable Root FS on NFS in defconfig
Ralink:
- Add Mediatek MT7628A SoC
- Allow NULL clock for clk_get_rate
- Explicitly request exclusive reset control in the pci-mt7620 PCI driver.
SEAD3:
- Only include in 32 bit kernels by default
VoCore:
- Add VoCore as a vendor t0 dt-bindings
- Add defconfig file"
* '4.14-features' of git://git.linux-mips.org/pub/scm/ralf/upstream-linus: (167 commits)
MIPS: Refactor handling of stack pointer in get_frame_info
MIPS: Stacktrace: Fix microMIPS stack unwinding on big endian systems
MIPS: microMIPS: Fix decoding of swsp16 instruction
MIPS: microMIPS: Fix decoding of addiusp instruction
MIPS: microMIPS: Fix detection of addiusp instruction
MIPS: Handle non word sized instructions when examining frame
MIPS: ralink: allow NULL clock for clk_get_rate
MIPS: Loongson 2F: allow NULL clock for clk_get_rate
MIPS: BCM63XX: allow NULL clock for clk_get_rate
MIPS: AR7: allow NULL clock for clk_get_rate
MIPS: BCM63XX: fix ENETDMA_6345_MAXBURST_REG offset
mips: Save all registers when saving the frame
MIPS: Add DWARF unwinding to assembly
MIPS: Make SAVE_SOME more standard
MIPS: Fix issues in backtraces
MIPS: jz4780: DTS: Probe the jz4740-rtc driver from devicetree
MIPS: Ci20: Enable RTC driver
watchdog: octeon-wdt: Add support for 78XX SOCs.
watchdog: octeon-wdt: Add support for cn68XX SOCs.
watchdog: octeon-wdt: File cleaning.
...
140 lines
3.7 KiB
Plaintext
140 lines
3.7 KiB
Plaintext
config ARCH_HAS_RESET_CONTROLLER
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bool
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menuconfig RESET_CONTROLLER
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bool "Reset Controller Support"
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default y if ARCH_HAS_RESET_CONTROLLER
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help
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Generic Reset Controller support.
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This framework is designed to abstract reset handling of devices
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via GPIOs or SoC-internal reset controller modules.
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If unsure, say no.
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if RESET_CONTROLLER
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config RESET_A10SR
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tristate "Altera Arria10 System Resource Reset"
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depends on MFD_ALTERA_A10SR
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help
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This option enables support for the external reset functions for
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peripheral PHYs on the Altera Arria10 System Resource Chip.
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config RESET_ATH79
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bool "AR71xx Reset Driver" if COMPILE_TEST
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default ATH79
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help
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This enables the ATH79 reset controller driver that supports the
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AR71xx SoC reset controller.
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config RESET_BERLIN
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bool "Berlin Reset Driver" if COMPILE_TEST
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default ARCH_BERLIN
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help
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This enables the reset controller driver for Marvell Berlin SoCs.
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config RESET_HSDK_V1
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bool "HSDK v1 Reset Driver"
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default n
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help
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This enables the reset controller driver for HSDK v1.
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config RESET_IMX7
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bool "i.MX7 Reset Driver" if COMPILE_TEST
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default SOC_IMX7D
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select MFD_SYSCON
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help
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This enables the reset controller driver for i.MX7 SoCs.
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config RESET_LANTIQ
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bool "Lantiq XWAY Reset Driver" if COMPILE_TEST
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default SOC_TYPE_XWAY
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help
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This enables the reset controller driver for Lantiq / Intel XWAY SoCs.
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config RESET_LPC18XX
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bool "LPC18xx/43xx Reset Driver" if COMPILE_TEST
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default ARCH_LPC18XX
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help
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This enables the reset controller driver for NXP LPC18xx/43xx SoCs.
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config RESET_MESON
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bool "Meson Reset Driver" if COMPILE_TEST
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default ARCH_MESON
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help
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This enables the reset driver for Amlogic Meson SoCs.
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config RESET_OXNAS
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bool
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config RESET_PISTACHIO
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bool "Pistachio Reset Driver" if COMPILE_TEST
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default MACH_PISTACHIO
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help
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This enables the reset driver for ImgTec Pistachio SoCs.
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config RESET_SOCFPGA
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bool "SoCFPGA Reset Driver" if COMPILE_TEST
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default ARCH_SOCFPGA
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help
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This enables the reset controller driver for Altera SoCFPGAs.
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config RESET_STM32
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bool "STM32 Reset Driver" if COMPILE_TEST
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default ARCH_STM32
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help
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This enables the RCC reset controller driver for STM32 MCUs.
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config RESET_SUNXI
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bool "Allwinner SoCs Reset Driver" if COMPILE_TEST && !ARCH_SUNXI
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default ARCH_SUNXI
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help
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This enables the reset driver for Allwinner SoCs.
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config RESET_TI_SCI
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tristate "TI System Control Interface (TI-SCI) reset driver"
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depends on TI_SCI_PROTOCOL
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help
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This enables the reset driver support over TI System Control Interface
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available on some new TI's SoCs. If you wish to use reset resources
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managed by the TI System Controller, say Y here. Otherwise, say N.
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config RESET_TI_SYSCON
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tristate "TI SYSCON Reset Driver"
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depends on HAS_IOMEM
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select MFD_SYSCON
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help
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This enables the reset driver support for TI devices with
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memory-mapped reset registers as part of a syscon device node. If
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you wish to use the reset framework for such memory-mapped devices,
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say Y here. Otherwise, say N.
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config RESET_UNIPHIER
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tristate "Reset controller driver for UniPhier SoCs"
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depends on ARCH_UNIPHIER || COMPILE_TEST
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depends on OF && MFD_SYSCON
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default ARCH_UNIPHIER
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help
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Support for reset controllers on UniPhier SoCs.
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Say Y if you want to control reset signals provided by System Control
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block, Media I/O block, Peripheral Block.
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config RESET_ZX2967
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bool "ZTE ZX2967 Reset Driver"
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depends on ARCH_ZX || COMPILE_TEST
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help
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This enables the reset controller driver for ZTE's zx2967 family.
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config RESET_ZYNQ
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bool "ZYNQ Reset Driver" if COMPILE_TEST
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default ARCH_ZYNQ
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help
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This enables the reset controller driver for Xilinx Zynq SoCs.
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source "drivers/reset/sti/Kconfig"
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source "drivers/reset/hisilicon/Kconfig"
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source "drivers/reset/tegra/Kconfig"
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endif
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