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https://github.com/AuxXxilium/linux_dsm_epyc7002.git
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57b317f912
The fout clock of BPLL and MPLL have a selectable source on EXYNOS5250. The clock options are a fixed divided by 2 clock and the output of the PLL itself. Add support for these new clock instances. Signed-off-by: Kisoo Yu <ksoo.yu@samsung.com> Signed-off-by: Thomas Abraham <thomas.abraham@linaro.org> [kgene.kim@samsung.com: moved common pll stuff into s5p-clock.c] Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
66 lines
2.2 KiB
C
66 lines
2.2 KiB
C
/* linux/arch/arm/plat-samsung/include/plat/s5p-clock.h
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*
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* Copyright (c) 2009-2010 Samsung Electronics Co., Ltd.
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* http://www.samsung.com
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*
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* Header file for s5p clock support
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*/
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#ifndef __ASM_PLAT_S5P_CLOCK_H
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#define __ASM_PLAT_S5P_CLOCK_H __FILE__
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#include <linux/clk.h>
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#define GET_DIV(clk, field) ((((clk) & field##_MASK) >> field##_SHIFT) + 1)
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#define clk_fin_apll clk_ext_xtal_mux
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#define clk_fin_bpll clk_ext_xtal_mux
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#define clk_fin_cpll clk_ext_xtal_mux
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#define clk_fin_mpll clk_ext_xtal_mux
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#define clk_fin_epll clk_ext_xtal_mux
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#define clk_fin_dpll clk_ext_xtal_mux
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#define clk_fin_vpll clk_ext_xtal_mux
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#define clk_fin_hpll clk_ext_xtal_mux
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extern struct clk clk_ext_xtal_mux;
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extern struct clk clk_xusbxti;
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extern struct clk clk_48m;
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extern struct clk s5p_clk_27m;
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extern struct clk clk_fout_apll;
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extern struct clk clk_fout_bpll;
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extern struct clk clk_fout_bpll_div2;
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extern struct clk clk_fout_cpll;
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extern struct clk clk_fout_mpll;
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extern struct clk clk_fout_mpll_div2;
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extern struct clk clk_fout_epll;
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extern struct clk clk_fout_dpll;
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extern struct clk clk_fout_vpll;
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extern struct clk clk_arm;
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extern struct clk clk_vpll;
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extern struct clksrc_sources clk_src_apll;
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extern struct clksrc_sources clk_src_bpll;
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extern struct clksrc_sources clk_src_bpll_fout;
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extern struct clksrc_sources clk_src_cpll;
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extern struct clksrc_sources clk_src_mpll;
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extern struct clksrc_sources clk_src_mpll_fout;
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extern struct clksrc_sources clk_src_epll;
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extern struct clksrc_sources clk_src_dpll;
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extern int s5p_gatectrl(void __iomem *reg, struct clk *clk, int enable);
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/* Common EPLL operations for S5P platform */
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extern int s5p_epll_enable(struct clk *clk, int enable);
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extern unsigned long s5p_epll_get_rate(struct clk *clk);
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/* SPDIF clk operations common for S5PC100/V210/C110 and Exynos4 */
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extern int s5p_spdif_set_rate(struct clk *clk, unsigned long rate);
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extern unsigned long s5p_spdif_get_rate(struct clk *clk);
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extern struct clk_ops s5p_sclk_spdif_ops;
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#endif /* __ASM_PLAT_S5P_CLOCK_H */
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