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f8d9f92452
It can be useful for JIT software to be aware of MIDR_EL1 and REVIDR_EL1 to ascertain the presence of any core errata that could affect code generation. This patch exposes these registers through sysfs: /sys/devices/system/cpu/cpu$ID/regs/identification/midr_el1 /sys/devices/system/cpu/cpu$ID/regs/identification/revidr_el1 where $ID is the cpu number. For big.LITTLE systems, one can have a mixture of cores (e.g. Cortex A53 and Cortex A57), thus all CPUs need to be enumerated. If the kernel does not have valid information to populate these entries with, an empty string is returned to userspace. Cc: Mark Rutland <mark.rutland@arm.com> Reviewed-by: Will Deacon <will.deacon@arm.com> Signed-off-by: Steve Capper <steve.capper@linaro.org> [suzuki.poulose@arm.com: ABI documentation updates, hotplug notifiers, kobject changes] Signed-off-by: Suzuki K Poulose <suzuki.poulose@arm.com> Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
74 lines
1.7 KiB
C
74 lines
1.7 KiB
C
/*
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* Copyright (C) 2014 ARM Ltd.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program. If not, see <http://www.gnu.org/licenses/>.
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*/
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#ifndef __ASM_CPU_H
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#define __ASM_CPU_H
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#include <linux/cpu.h>
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#include <linux/init.h>
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#include <linux/percpu.h>
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/*
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* Records attributes of an individual CPU.
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*/
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struct cpuinfo_arm64 {
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struct cpu cpu;
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struct kobject kobj;
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u32 reg_ctr;
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u32 reg_cntfrq;
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u32 reg_dczid;
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u32 reg_midr;
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u32 reg_revidr;
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u64 reg_id_aa64dfr0;
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u64 reg_id_aa64dfr1;
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u64 reg_id_aa64isar0;
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u64 reg_id_aa64isar1;
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u64 reg_id_aa64mmfr0;
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u64 reg_id_aa64mmfr1;
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u64 reg_id_aa64mmfr2;
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u64 reg_id_aa64pfr0;
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u64 reg_id_aa64pfr1;
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u32 reg_id_dfr0;
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u32 reg_id_isar0;
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u32 reg_id_isar1;
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u32 reg_id_isar2;
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u32 reg_id_isar3;
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u32 reg_id_isar4;
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u32 reg_id_isar5;
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u32 reg_id_mmfr0;
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u32 reg_id_mmfr1;
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u32 reg_id_mmfr2;
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u32 reg_id_mmfr3;
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u32 reg_id_pfr0;
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u32 reg_id_pfr1;
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u32 reg_mvfr0;
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u32 reg_mvfr1;
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u32 reg_mvfr2;
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};
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DECLARE_PER_CPU(struct cpuinfo_arm64, cpu_data);
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void cpuinfo_store_cpu(void);
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void __init cpuinfo_store_boot_cpu(void);
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void __init init_cpu_features(struct cpuinfo_arm64 *info);
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void update_cpu_features(int cpu, struct cpuinfo_arm64 *info,
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struct cpuinfo_arm64 *boot);
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#endif /* __ASM_CPU_H */
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