mirror of
https://github.com/AuxXxilium/linux_dsm_epyc7002.git
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b24413180f
Many source files in the tree are missing licensing information, which makes it harder for compliance tools to determine the correct license. By default all files without license information are under the default license of the kernel, which is GPL version 2. Update the files which contain no license information with the 'GPL-2.0' SPDX license identifier. The SPDX identifier is a legally binding shorthand, which can be used instead of the full boiler plate text. This patch is based on work done by Thomas Gleixner and Kate Stewart and Philippe Ombredanne. How this work was done: Patches were generated and checked against linux-4.14-rc6 for a subset of the use cases: - file had no licensing information it it. - file was a */uapi/* one with no licensing information in it, - file was a */uapi/* one with existing licensing information, Further patches will be generated in subsequent months to fix up cases where non-standard license headers were used, and references to license had to be inferred by heuristics based on keywords. The analysis to determine which SPDX License Identifier to be applied to a file was done in a spreadsheet of side by side results from of the output of two independent scanners (ScanCode & Windriver) producing SPDX tag:value files created by Philippe Ombredanne. Philippe prepared the base worksheet, and did an initial spot review of a few 1000 files. The 4.13 kernel was the starting point of the analysis with 60,537 files assessed. Kate Stewart did a file by file comparison of the scanner results in the spreadsheet to determine which SPDX license identifier(s) to be applied to the file. She confirmed any determination that was not immediately clear with lawyers working with the Linux Foundation. Criteria used to select files for SPDX license identifier tagging was: - Files considered eligible had to be source code files. - Make and config files were included as candidates if they contained >5 lines of source - File already had some variant of a license header in it (even if <5 lines). All documentation files were explicitly excluded. The following heuristics were used to determine which SPDX license identifiers to apply. - when both scanners couldn't find any license traces, file was considered to have no license information in it, and the top level COPYING file license applied. For non */uapi/* files that summary was: SPDX license identifier # files ---------------------------------------------------|------- GPL-2.0 11139 and resulted in the first patch in this series. If that file was a */uapi/* path one, it was "GPL-2.0 WITH Linux-syscall-note" otherwise it was "GPL-2.0". Results of that was: SPDX license identifier # files ---------------------------------------------------|------- GPL-2.0 WITH Linux-syscall-note 930 and resulted in the second patch in this series. - if a file had some form of licensing information in it, and was one of the */uapi/* ones, it was denoted with the Linux-syscall-note if any GPL family license was found in the file or had no licensing in it (per prior point). Results summary: SPDX license identifier # files ---------------------------------------------------|------ GPL-2.0 WITH Linux-syscall-note 270 GPL-2.0+ WITH Linux-syscall-note 169 ((GPL-2.0 WITH Linux-syscall-note) OR BSD-2-Clause) 21 ((GPL-2.0 WITH Linux-syscall-note) OR BSD-3-Clause) 17 LGPL-2.1+ WITH Linux-syscall-note 15 GPL-1.0+ WITH Linux-syscall-note 14 ((GPL-2.0+ WITH Linux-syscall-note) OR BSD-3-Clause) 5 LGPL-2.0+ WITH Linux-syscall-note 4 LGPL-2.1 WITH Linux-syscall-note 3 ((GPL-2.0 WITH Linux-syscall-note) OR MIT) 3 ((GPL-2.0 WITH Linux-syscall-note) AND MIT) 1 and that resulted in the third patch in this series. - when the two scanners agreed on the detected license(s), that became the concluded license(s). - when there was disagreement between the two scanners (one detected a license but the other didn't, or they both detected different licenses) a manual inspection of the file occurred. - In most cases a manual inspection of the information in the file resulted in a clear resolution of the license that should apply (and which scanner probably needed to revisit its heuristics). - When it was not immediately clear, the license identifier was confirmed with lawyers working with the Linux Foundation. - If there was any question as to the appropriate license identifier, the file was flagged for further research and to be revisited later in time. In total, over 70 hours of logged manual review was done on the spreadsheet to determine the SPDX license identifiers to apply to the source files by Kate, Philippe, Thomas and, in some cases, confirmation by lawyers working with the Linux Foundation. Kate also obtained a third independent scan of the 4.13 code base from FOSSology, and compared selected files where the other two scanners disagreed against that SPDX file, to see if there was new insights. The Windriver scanner is based on an older version of FOSSology in part, so they are related. Thomas did random spot checks in about 500 files from the spreadsheets for the uapi headers and agreed with SPDX license identifier in the files he inspected. For the non-uapi files Thomas did random spot checks in about 15000 files. In initial set of patches against 4.14-rc6, 3 files were found to have copy/paste license identifier errors, and have been fixed to reflect the correct identifier. Additionally Philippe spent 10 hours this week doing a detailed manual inspection and review of the 12,461 patched files from the initial patch version early this week with: - a full scancode scan run, collecting the matched texts, detected license ids and scores - reviewing anything where there was a license detected (about 500+ files) to ensure that the applied SPDX license was correct - reviewing anything where there was no detection but the patch license was not GPL-2.0 WITH Linux-syscall-note to ensure that the applied SPDX license was correct This produced a worksheet with 20 files needing minor correction. This worksheet was then exported into 3 different .csv files for the different types of files to be modified. These .csv files were then reviewed by Greg. Thomas wrote a script to parse the csv files and add the proper SPDX tag to the file, in the format that the file expected. This script was further refined by Greg based on the output to detect more types of files automatically and to distinguish between header and source .c files (which need different comment types.) Finally Greg ran the script using the .csv files to generate the patches. Reviewed-by: Kate Stewart <kstewart@linuxfoundation.org> Reviewed-by: Philippe Ombredanne <pombredanne@nexb.com> Reviewed-by: Thomas Gleixner <tglx@linutronix.de> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
586 lines
12 KiB
C
586 lines
12 KiB
C
// SPDX-License-Identifier: GPL-2.0
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/*
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* align.c - address exception handler for M32R
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*
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* Copyright (c) 2003 Hitoshi Yamamoto
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*/
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#include <asm/ptrace.h>
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#include <linux/uaccess.h>
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static int get_reg(struct pt_regs *regs, int nr)
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{
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int val;
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if (nr < 4)
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val = *(unsigned long *)(®s->r0 + nr);
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else if (nr < 7)
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val = *(unsigned long *)(®s->r4 + (nr - 4));
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else if (nr < 13)
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val = *(unsigned long *)(®s->r7 + (nr - 7));
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else
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val = *(unsigned long *)(®s->fp + (nr - 13));
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return val;
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}
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static void set_reg(struct pt_regs *regs, int nr, int val)
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{
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if (nr < 4)
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*(unsigned long *)(®s->r0 + nr) = val;
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else if (nr < 7)
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*(unsigned long *)(®s->r4 + (nr - 4)) = val;
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else if (nr < 13)
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*(unsigned long *)(®s->r7 + (nr - 7)) = val;
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else
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*(unsigned long *)(®s->fp + (nr - 13)) = val;
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}
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#define REG1(insn) (((insn) & 0x0f00) >> 8)
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#define REG2(insn) ((insn) & 0x000f)
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#define PSW_BC 0x100
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/* O- instruction */
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#define ISA_LD1 0x20c0 /* ld Rdest, @Rsrc */
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#define ISA_LD2 0x20e0 /* ld Rdest, @Rsrc+ */
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#define ISA_LDH 0x20a0 /* ldh Rdest, @Rsrc */
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#define ISA_LDUH 0x20b0 /* lduh Rdest, @Rsrc */
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#define ISA_ST1 0x2040 /* st Rsrc1, @Rsrc2 */
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#define ISA_ST2 0x2060 /* st Rsrc1, @+Rsrc2 */
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#define ISA_ST3 0x2070 /* st Rsrc1, @-Rsrc2 */
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#define ISA_STH1 0x2020 /* sth Rsrc1, @Rsrc2 */
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#define ISA_STH2 0x2030 /* sth Rsrc1, @Rsrc2+ */
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#ifdef CONFIG_ISA_DUAL_ISSUE
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/* OS instruction */
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#define ISA_ADD 0x00a0 /* add Rdest, Rsrc */
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#define ISA_ADDI 0x4000 /* addi Rdest, #imm8 */
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#define ISA_ADDX 0x0090 /* addx Rdest, Rsrc */
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#define ISA_AND 0x00c0 /* and Rdest, Rsrc */
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#define ISA_CMP 0x0040 /* cmp Rsrc1, Rsrc2 */
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#define ISA_CMPEQ 0x0060 /* cmpeq Rsrc1, Rsrc2 */
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#define ISA_CMPU 0x0050 /* cmpu Rsrc1, Rsrc2 */
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#define ISA_CMPZ 0x0070 /* cmpz Rsrc */
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#define ISA_LDI 0x6000 /* ldi Rdest, #imm8 */
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#define ISA_MV 0x1080 /* mv Rdest, Rsrc */
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#define ISA_NEG 0x0030 /* neg Rdest, Rsrc */
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#define ISA_NOP 0x7000 /* nop */
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#define ISA_NOT 0x00b0 /* not Rdest, Rsrc */
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#define ISA_OR 0x00e0 /* or Rdest, Rsrc */
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#define ISA_SUB 0x0020 /* sub Rdest, Rsrc */
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#define ISA_SUBX 0x0010 /* subx Rdest, Rsrc */
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#define ISA_XOR 0x00d0 /* xor Rdest, Rsrc */
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/* -S instruction */
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#define ISA_MUL 0x1060 /* mul Rdest, Rsrc */
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#define ISA_MULLO_A0 0x3010 /* mullo Rsrc1, Rsrc2, A0 */
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#define ISA_MULLO_A1 0x3090 /* mullo Rsrc1, Rsrc2, A1 */
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#define ISA_MVFACMI_A0 0x50f2 /* mvfacmi Rdest, A0 */
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#define ISA_MVFACMI_A1 0x50f6 /* mvfacmi Rdest, A1 */
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static int emu_addi(unsigned short insn, struct pt_regs *regs)
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{
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char imm = (char)(insn & 0xff);
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int dest = REG1(insn);
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int val;
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val = get_reg(regs, dest);
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val += imm;
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set_reg(regs, dest, val);
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return 0;
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}
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static int emu_ldi(unsigned short insn, struct pt_regs *regs)
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{
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char imm = (char)(insn & 0xff);
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set_reg(regs, REG1(insn), (int)imm);
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return 0;
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}
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static int emu_add(unsigned short insn, struct pt_regs *regs)
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{
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int dest = REG1(insn);
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int src = REG2(insn);
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int val;
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val = get_reg(regs, dest);
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val += get_reg(regs, src);
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set_reg(regs, dest, val);
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return 0;
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}
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static int emu_addx(unsigned short insn, struct pt_regs *regs)
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{
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int dest = REG1(insn);
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unsigned int val, tmp;
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val = regs->psw & PSW_BC ? 1 : 0;
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tmp = get_reg(regs, dest);
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val += tmp;
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val += (unsigned int)get_reg(regs, REG2(insn));
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set_reg(regs, dest, val);
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/* C bit set */
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if (val < tmp)
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regs->psw |= PSW_BC;
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else
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regs->psw &= ~(PSW_BC);
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return 0;
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}
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static int emu_and(unsigned short insn, struct pt_regs *regs)
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{
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int dest = REG1(insn);
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int val;
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val = get_reg(regs, dest);
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val &= get_reg(regs, REG2(insn));
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set_reg(regs, dest, val);
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return 0;
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}
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static int emu_cmp(unsigned short insn, struct pt_regs *regs)
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{
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if (get_reg(regs, REG1(insn)) < get_reg(regs, REG2(insn)))
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regs->psw |= PSW_BC;
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else
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regs->psw &= ~(PSW_BC);
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return 0;
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}
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static int emu_cmpeq(unsigned short insn, struct pt_regs *regs)
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{
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if (get_reg(regs, REG1(insn)) == get_reg(regs, REG2(insn)))
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regs->psw |= PSW_BC;
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else
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regs->psw &= ~(PSW_BC);
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return 0;
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}
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static int emu_cmpu(unsigned short insn, struct pt_regs *regs)
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{
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if ((unsigned int)get_reg(regs, REG1(insn))
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< (unsigned int)get_reg(regs, REG2(insn)))
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regs->psw |= PSW_BC;
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else
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regs->psw &= ~(PSW_BC);
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return 0;
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}
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static int emu_cmpz(unsigned short insn, struct pt_regs *regs)
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{
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if (!get_reg(regs, REG2(insn)))
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regs->psw |= PSW_BC;
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else
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regs->psw &= ~(PSW_BC);
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return 0;
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}
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static int emu_mv(unsigned short insn, struct pt_regs *regs)
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{
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int val;
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val = get_reg(regs, REG2(insn));
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set_reg(regs, REG1(insn), val);
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return 0;
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}
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static int emu_neg(unsigned short insn, struct pt_regs *regs)
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{
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int val;
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val = get_reg(regs, REG2(insn));
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set_reg(regs, REG1(insn), 0 - val);
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return 0;
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}
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static int emu_not(unsigned short insn, struct pt_regs *regs)
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{
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int val;
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val = get_reg(regs, REG2(insn));
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set_reg(regs, REG1(insn), ~val);
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return 0;
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}
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static int emu_or(unsigned short insn, struct pt_regs *regs)
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{
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int dest = REG1(insn);
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int val;
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val = get_reg(regs, dest);
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val |= get_reg(regs, REG2(insn));
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set_reg(regs, dest, val);
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return 0;
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}
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static int emu_sub(unsigned short insn, struct pt_regs *regs)
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{
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int dest = REG1(insn);
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int val;
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val = get_reg(regs, dest);
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val -= get_reg(regs, REG2(insn));
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set_reg(regs, dest, val);
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return 0;
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}
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static int emu_subx(unsigned short insn, struct pt_regs *regs)
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{
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int dest = REG1(insn);
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unsigned int val, tmp;
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val = tmp = get_reg(regs, dest);
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val -= (unsigned int)get_reg(regs, REG2(insn));
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val -= regs->psw & PSW_BC ? 1 : 0;
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set_reg(regs, dest, val);
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/* C bit set */
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if (val > tmp)
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regs->psw |= PSW_BC;
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else
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regs->psw &= ~(PSW_BC);
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return 0;
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}
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static int emu_xor(unsigned short insn, struct pt_regs *regs)
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{
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int dest = REG1(insn);
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unsigned int val;
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val = (unsigned int)get_reg(regs, dest);
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val ^= (unsigned int)get_reg(regs, REG2(insn));
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set_reg(regs, dest, val);
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return 0;
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}
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static int emu_mul(unsigned short insn, struct pt_regs *regs)
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{
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int dest = REG1(insn);
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int reg1, reg2;
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reg1 = get_reg(regs, dest);
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reg2 = get_reg(regs, REG2(insn));
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__asm__ __volatile__ (
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"mul %0, %1; \n\t"
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: "+r" (reg1) : "r" (reg2)
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);
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set_reg(regs, dest, reg1);
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return 0;
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}
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static int emu_mullo_a0(unsigned short insn, struct pt_regs *regs)
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{
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int reg1, reg2;
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reg1 = get_reg(regs, REG1(insn));
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reg2 = get_reg(regs, REG2(insn));
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__asm__ __volatile__ (
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"mullo %0, %1, a0; \n\t"
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"mvfachi %0, a0; \n\t"
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"mvfaclo %1, a0; \n\t"
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: "+r" (reg1), "+r" (reg2)
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);
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regs->acc0h = reg1;
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regs->acc0l = reg2;
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return 0;
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}
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static int emu_mullo_a1(unsigned short insn, struct pt_regs *regs)
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{
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int reg1, reg2;
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reg1 = get_reg(regs, REG1(insn));
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reg2 = get_reg(regs, REG2(insn));
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__asm__ __volatile__ (
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"mullo %0, %1, a0; \n\t"
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"mvfachi %0, a0; \n\t"
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"mvfaclo %1, a0; \n\t"
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: "+r" (reg1), "+r" (reg2)
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);
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regs->acc1h = reg1;
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regs->acc1l = reg2;
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return 0;
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}
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static int emu_mvfacmi_a0(unsigned short insn, struct pt_regs *regs)
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{
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unsigned long val;
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val = (regs->acc0h << 16) | (regs->acc0l >> 16);
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set_reg(regs, REG1(insn), (int)val);
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return 0;
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}
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static int emu_mvfacmi_a1(unsigned short insn, struct pt_regs *regs)
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{
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unsigned long val;
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val = (regs->acc1h << 16) | (regs->acc1l >> 16);
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set_reg(regs, REG1(insn), (int)val);
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return 0;
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}
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static int emu_m32r2(unsigned short insn, struct pt_regs *regs)
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{
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int res = -1;
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if ((insn & 0x7fff) == ISA_NOP) /* nop */
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return 0;
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switch(insn & 0x7000) {
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case ISA_ADDI: /* addi Rdest, #imm8 */
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res = emu_addi(insn, regs);
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break;
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case ISA_LDI: /* ldi Rdest, #imm8 */
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res = emu_ldi(insn, regs);
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break;
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default:
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break;
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}
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if (!res)
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return 0;
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switch(insn & 0x70f0) {
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case ISA_ADD: /* add Rdest, Rsrc */
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res = emu_add(insn, regs);
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break;
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case ISA_ADDX: /* addx Rdest, Rsrc */
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res = emu_addx(insn, regs);
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break;
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case ISA_AND: /* and Rdest, Rsrc */
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res = emu_and(insn, regs);
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break;
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case ISA_CMP: /* cmp Rsrc1, Rsrc2 */
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res = emu_cmp(insn, regs);
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break;
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case ISA_CMPEQ: /* cmpeq Rsrc1, Rsrc2 */
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res = emu_cmpeq(insn, regs);
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break;
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case ISA_CMPU: /* cmpu Rsrc1, Rsrc2 */
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res = emu_cmpu(insn, regs);
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break;
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case ISA_CMPZ: /* cmpz Rsrc */
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res = emu_cmpz(insn, regs);
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break;
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case ISA_MV: /* mv Rdest, Rsrc */
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res = emu_mv(insn, regs);
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break;
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case ISA_NEG: /* neg Rdest, Rsrc */
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res = emu_neg(insn, regs);
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break;
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case ISA_NOT: /* not Rdest, Rsrc */
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res = emu_not(insn, regs);
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break;
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case ISA_OR: /* or Rdest, Rsrc */
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res = emu_or(insn, regs);
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break;
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case ISA_SUB: /* sub Rdest, Rsrc */
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res = emu_sub(insn, regs);
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break;
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case ISA_SUBX: /* subx Rdest, Rsrc */
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res = emu_subx(insn, regs);
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break;
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case ISA_XOR: /* xor Rdest, Rsrc */
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res = emu_xor(insn, regs);
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break;
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case ISA_MUL: /* mul Rdest, Rsrc */
|
|
res = emu_mul(insn, regs);
|
|
break;
|
|
case ISA_MULLO_A0: /* mullo Rsrc1, Rsrc2 */
|
|
res = emu_mullo_a0(insn, regs);
|
|
break;
|
|
case ISA_MULLO_A1: /* mullo Rsrc1, Rsrc2 */
|
|
res = emu_mullo_a1(insn, regs);
|
|
break;
|
|
default:
|
|
break;
|
|
}
|
|
|
|
if (!res)
|
|
return 0;
|
|
|
|
switch(insn & 0x70ff) {
|
|
case ISA_MVFACMI_A0: /* mvfacmi Rdest */
|
|
res = emu_mvfacmi_a0(insn, regs);
|
|
break;
|
|
case ISA_MVFACMI_A1: /* mvfacmi Rdest */
|
|
res = emu_mvfacmi_a1(insn, regs);
|
|
break;
|
|
default:
|
|
break;
|
|
}
|
|
|
|
return res;
|
|
}
|
|
|
|
#endif /* CONFIG_ISA_DUAL_ISSUE */
|
|
|
|
/*
|
|
* ld : ?010 dest 1100 src
|
|
* 0010 dest 1110 src : ld Rdest, @Rsrc+
|
|
* ldh : ?010 dest 1010 src
|
|
* lduh : ?010 dest 1011 src
|
|
* st : ?010 src1 0100 src2
|
|
* 0010 src1 0110 src2 : st Rsrc1, @+Rsrc2
|
|
* 0010 src1 0111 src2 : st Rsrc1, @-Rsrc2
|
|
* sth : ?010 src1 0010 src2
|
|
*/
|
|
|
|
static int insn_check(unsigned long insn, struct pt_regs *regs,
|
|
unsigned char **ucp)
|
|
{
|
|
int res = 0;
|
|
|
|
/*
|
|
* 32bit insn
|
|
* ld Rdest, @(disp16, Rsrc)
|
|
* st Rdest, @(disp16, Rsrc)
|
|
*/
|
|
if (insn & 0x80000000) { /* 32bit insn */
|
|
*ucp += (short)(insn & 0x0000ffff);
|
|
regs->bpc += 4;
|
|
} else { /* 16bit insn */
|
|
#ifdef CONFIG_ISA_DUAL_ISSUE
|
|
/* parallel exec check */
|
|
if (!(regs->bpc & 0x2) && insn & 0x8000) {
|
|
res = emu_m32r2((unsigned short)insn, regs);
|
|
regs->bpc += 4;
|
|
} else
|
|
#endif /* CONFIG_ISA_DUAL_ISSUE */
|
|
regs->bpc += 2;
|
|
}
|
|
|
|
return res;
|
|
}
|
|
|
|
static int emu_ld(unsigned long insn32, struct pt_regs *regs)
|
|
{
|
|
unsigned char *ucp;
|
|
unsigned long val;
|
|
unsigned short insn16;
|
|
int size, src;
|
|
|
|
insn16 = insn32 >> 16;
|
|
src = REG2(insn16);
|
|
ucp = (unsigned char *)get_reg(regs, src);
|
|
|
|
if (insn_check(insn32, regs, &ucp))
|
|
return -1;
|
|
|
|
size = insn16 & 0x0040 ? 4 : 2;
|
|
if (copy_from_user(&val, ucp, size))
|
|
return -1;
|
|
|
|
if (size == 2)
|
|
val >>= 16;
|
|
|
|
/* ldh sign check */
|
|
if ((insn16 & 0x00f0) == 0x00a0 && (val & 0x8000))
|
|
val |= 0xffff0000;
|
|
|
|
set_reg(regs, REG1(insn16), val);
|
|
|
|
/* ld increment check */
|
|
if ((insn16 & 0xf0f0) == ISA_LD2) /* ld Rdest, @Rsrc+ */
|
|
set_reg(regs, src, (unsigned long)(ucp + 4));
|
|
|
|
return 0;
|
|
}
|
|
|
|
static int emu_st(unsigned long insn32, struct pt_regs *regs)
|
|
{
|
|
unsigned char *ucp;
|
|
unsigned long val;
|
|
unsigned short insn16;
|
|
int size, src2;
|
|
|
|
insn16 = insn32 >> 16;
|
|
src2 = REG2(insn16);
|
|
|
|
ucp = (unsigned char *)get_reg(regs, src2);
|
|
|
|
if (insn_check(insn32, regs, &ucp))
|
|
return -1;
|
|
|
|
size = insn16 & 0x0040 ? 4 : 2;
|
|
val = get_reg(regs, REG1(insn16));
|
|
if (size == 2)
|
|
val <<= 16;
|
|
|
|
/* st inc/dec check */
|
|
if ((insn16 & 0xf0e0) == 0x2060) {
|
|
if (insn16 & 0x0010)
|
|
ucp -= 4;
|
|
else
|
|
ucp += 4;
|
|
|
|
set_reg(regs, src2, (unsigned long)ucp);
|
|
}
|
|
|
|
if (copy_to_user(ucp, &val, size))
|
|
return -1;
|
|
|
|
/* sth inc check */
|
|
if ((insn16 & 0xf0f0) == ISA_STH2) {
|
|
ucp += 2;
|
|
set_reg(regs, src2, (unsigned long)ucp);
|
|
}
|
|
|
|
return 0;
|
|
}
|
|
|
|
int handle_unaligned_access(unsigned long insn32, struct pt_regs *regs)
|
|
{
|
|
unsigned short insn16;
|
|
int res;
|
|
|
|
insn16 = insn32 >> 16;
|
|
|
|
/* ld or st check */
|
|
if ((insn16 & 0x7000) != 0x2000)
|
|
return -1;
|
|
|
|
/* insn alignment check */
|
|
if ((insn16 & 0x8000) && (regs->bpc & 3))
|
|
return -1;
|
|
|
|
if (insn16 & 0x0080) /* ld */
|
|
res = emu_ld(insn32, regs);
|
|
else /* st */
|
|
res = emu_st(insn32, regs);
|
|
|
|
return res;
|
|
}
|
|
|