Punit Agrawal 0c09d48564 Documentation/arm64: HugeTLB page implementation ... Arm v8 architecture supports multiple page sizes - 4k, 16k and 64k. Based on the active page size, the Linux port supports corresponding hugepage sizes at PMD and PUD(4k only) levels. In addition, the architecture also supports caching larger sized ranges (composed of multiple entries) at the PTE and PMD level in the TLBs using the contiguous bit. The Linux port makes use of this architectural support to enable additional hugepage sizes. Describe the two different types of hugepages supported by the arm64 kernel and the hugepage sizes enabled by each. Acked-by: Randy Dunlap <rdunlap@infradead.org> Acked-by: Will Deacon <will.deacon@arm.com> Cc: Jonathan Corbet <corbet@lwn.net> Signed-off-by: Punit Agrawal <punit.agrawal@arm.com> Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>		2018-10-10 18:08:36 +01:00
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acpi_object_usage.txt
arm-acpi.txt
booting.txt
cpu-feature-registers.txt	arm64: Expose Arm v8.4 features	2018-03-19 18:14:27 +00:00
elf_hwcaps.txt	arm64: docs: Document SSBS HWCAP	2018-10-01 16:28:17 +01:00
hugetlbpage.txt	Documentation/arm64: HugeTLB page implementation	2018-10-10 18:08:36 +01:00
legacy_instructions.txt
memory.txt	arm64: KVM: Allow mapping of vectors outside of the RAM region	2018-03-19 13:06:46 +00:00
silicon-errata.txt	arm64: Add silicon-errata.txt entry for ARM erratum 1188873	2018-10-10 17:53:29 +01:00
sve.txt	Documentation/arm64/sve: Couple of improvements and typos	2018-08-29 11:33:19 +01:00
tagged-pointers.txt