mirror of
https://github.com/AuxXxilium/linux_dsm_epyc7002.git
synced 2025-02-23 14:45:34 +07:00
a9eab62d41
Apparently the hardware does not perform CCMP PN validation so
let mac80211 take care of possible replay attacks in sw.
Moreover indicate ICV and MIC had been stripped setting corresponding
bits in ieee80211_rx_status.
The fix has been validated using 4.2.1 and 4.1.3 tests from the WiFi
Alliance vulnerability detection tool.
Fixes: c869f77d6a ("add mt7601u driver")
Acked-by: Jakub Kicinski <kubakici@wp.pl>
Tested-by: David Park <david.park@hitemengineering.com>
Signed-off-by: Lorenzo Bianconi <lorenzo.bianconi@redhat.com>
Signed-off-by: Kalle Valo <kvalo@codeaurora.org>
166 lines
5.2 KiB
C
166 lines
5.2 KiB
C
/*
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* (c) Copyright 2002-2010, Ralink Technology, Inc.
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* Copyright (C) 2015 Jakub Kicinski <kubakici@wp.pl>
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2
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* as published by the Free Software Foundation
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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#ifndef __MT7601U_INITVALS_H
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#define __MT7601U_INITVALS_H
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static const struct mt76_reg_pair bbp_common_vals[] = {
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{ 65, 0x2c },
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{ 66, 0x38 },
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{ 68, 0x0b },
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{ 69, 0x12 },
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{ 70, 0x0a },
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{ 73, 0x10 },
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{ 81, 0x37 },
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{ 82, 0x62 },
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{ 83, 0x6a },
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{ 84, 0x99 },
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{ 86, 0x00 },
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{ 91, 0x04 },
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{ 92, 0x00 },
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{ 103, 0x00 },
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{ 105, 0x05 },
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{ 106, 0x35 },
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};
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static const struct mt76_reg_pair bbp_chip_vals[] = {
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{ 1, 0x04 }, { 4, 0x40 }, { 20, 0x06 }, { 31, 0x08 },
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/* CCK Tx Control */
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{ 178, 0xff },
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/* AGC/Sync controls */
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{ 66, 0x14 }, { 68, 0x8b }, { 69, 0x12 }, { 70, 0x09 },
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{ 73, 0x11 }, { 75, 0x60 }, { 76, 0x44 }, { 84, 0x9a },
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{ 86, 0x38 }, { 91, 0x07 }, { 92, 0x02 },
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/* Rx Path Controls */
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{ 99, 0x50 }, { 101, 0x00 }, { 103, 0xc0 }, { 104, 0x92 },
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{ 105, 0x3c }, { 106, 0x03 }, { 128, 0x12 },
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/* Change RXWI content: Gain Report */
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{ 142, 0x04 }, { 143, 0x37 },
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/* Change RXWI content: Antenna Report */
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{ 142, 0x03 }, { 143, 0x99 },
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/* Calibration Index Register */
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/* CCK Receiver Control */
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{ 160, 0xeb }, { 161, 0xc4 }, { 162, 0x77 }, { 163, 0xf9 },
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{ 164, 0x88 }, { 165, 0x80 }, { 166, 0xff }, { 167, 0xe4 },
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/* Added AGC controls - these AGC/GLRT registers are accessed
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* through R195 and R196.
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*/
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{ 195, 0x00 }, { 196, 0x00 },
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{ 195, 0x01 }, { 196, 0x04 },
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{ 195, 0x02 }, { 196, 0x20 },
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{ 195, 0x03 }, { 196, 0x0a },
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{ 195, 0x06 }, { 196, 0x16 },
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{ 195, 0x07 }, { 196, 0x05 },
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{ 195, 0x08 }, { 196, 0x37 },
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{ 195, 0x0a }, { 196, 0x15 },
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{ 195, 0x0b }, { 196, 0x17 },
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{ 195, 0x0c }, { 196, 0x06 },
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{ 195, 0x0d }, { 196, 0x09 },
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{ 195, 0x0e }, { 196, 0x05 },
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{ 195, 0x0f }, { 196, 0x09 },
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{ 195, 0x10 }, { 196, 0x20 },
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{ 195, 0x20 }, { 196, 0x17 },
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{ 195, 0x21 }, { 196, 0x06 },
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{ 195, 0x22 }, { 196, 0x09 },
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{ 195, 0x23 }, { 196, 0x17 },
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{ 195, 0x24 }, { 196, 0x06 },
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{ 195, 0x25 }, { 196, 0x09 },
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{ 195, 0x26 }, { 196, 0x17 },
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{ 195, 0x27 }, { 196, 0x06 },
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{ 195, 0x28 }, { 196, 0x09 },
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{ 195, 0x29 }, { 196, 0x05 },
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{ 195, 0x2a }, { 196, 0x09 },
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{ 195, 0x80 }, { 196, 0x8b },
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{ 195, 0x81 }, { 196, 0x12 },
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{ 195, 0x82 }, { 196, 0x09 },
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{ 195, 0x83 }, { 196, 0x17 },
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{ 195, 0x84 }, { 196, 0x11 },
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{ 195, 0x85 }, { 196, 0x00 },
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{ 195, 0x86 }, { 196, 0x00 },
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{ 195, 0x87 }, { 196, 0x18 },
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{ 195, 0x88 }, { 196, 0x60 },
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{ 195, 0x89 }, { 196, 0x44 },
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{ 195, 0x8a }, { 196, 0x8b },
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{ 195, 0x8b }, { 196, 0x8b },
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{ 195, 0x8c }, { 196, 0x8b },
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{ 195, 0x8d }, { 196, 0x8b },
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{ 195, 0x8e }, { 196, 0x09 },
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{ 195, 0x8f }, { 196, 0x09 },
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{ 195, 0x90 }, { 196, 0x09 },
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{ 195, 0x91 }, { 196, 0x09 },
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{ 195, 0x92 }, { 196, 0x11 },
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{ 195, 0x93 }, { 196, 0x11 },
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{ 195, 0x94 }, { 196, 0x11 },
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{ 195, 0x95 }, { 196, 0x11 },
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/* PPAD */
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{ 47, 0x80 }, { 60, 0x80 }, { 150, 0xd2 }, { 151, 0x32 },
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{ 152, 0x23 }, { 153, 0x41 }, { 154, 0x00 }, { 155, 0x4f },
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{ 253, 0x7e }, { 195, 0x30 }, { 196, 0x32 }, { 195, 0x31 },
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{ 196, 0x23 }, { 195, 0x32 }, { 196, 0x45 }, { 195, 0x35 },
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{ 196, 0x4a }, { 195, 0x36 }, { 196, 0x5a }, { 195, 0x37 },
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{ 196, 0x5a },
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};
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static const struct mt76_reg_pair mac_common_vals[] = {
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{ MT_LEGACY_BASIC_RATE, 0x0000013f },
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{ MT_HT_BASIC_RATE, 0x00008003 },
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{ MT_MAC_SYS_CTRL, 0x00000000 },
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{ MT_RX_FILTR_CFG, 0x00017f97 },
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{ MT_BKOFF_SLOT_CFG, 0x00000209 },
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{ MT_TX_SW_CFG0, 0x00000000 },
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{ MT_TX_SW_CFG1, 0x00080606 },
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{ MT_TX_LINK_CFG, 0x00001020 },
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{ MT_TX_TIMEOUT_CFG, 0x000a2090 },
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{ MT_MAX_LEN_CFG, 0x00003fff },
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{ MT_PBF_TX_MAX_PCNT, 0x1fbf1f1f },
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{ MT_PBF_RX_MAX_PCNT, 0x0000009f },
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{ MT_TX_RETRY_CFG, 0x47d01f0f },
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{ MT_AUTO_RSP_CFG, 0x00000013 },
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{ MT_CCK_PROT_CFG, 0x05740003 },
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{ MT_OFDM_PROT_CFG, 0x05740003 },
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{ MT_MM40_PROT_CFG, 0x03f44084 },
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{ MT_GF20_PROT_CFG, 0x01744004 },
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{ MT_GF40_PROT_CFG, 0x03f44084 },
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{ MT_MM20_PROT_CFG, 0x01744004 },
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{ MT_TXOP_CTRL_CFG, 0x0000583f },
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{ MT_TX_RTS_CFG, 0x01092b20 },
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{ MT_EXP_ACK_TIME, 0x002400ca },
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{ MT_TXOP_HLDR_ET, 0x00000002 },
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{ MT_XIFS_TIME_CFG, 0x33a41010 },
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{ MT_PWR_PIN_CFG, 0x00000000 },
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{ MT_PN_PAD_MODE, 0x00000001 },
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};
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static const struct mt76_reg_pair mac_chip_vals[] = {
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{ MT_TSO_CTRL, 0x00006050 },
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{ MT_BCN_OFFSET(0), 0x18100800 },
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{ MT_BCN_OFFSET(1), 0x38302820 },
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{ MT_PBF_SYS_CTRL, 0x00080c00 },
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{ MT_PBF_CFG, 0x7f723c1f },
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{ MT_FCE_PSE_CTRL, 0x00000001 },
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{ MT_PAUSE_ENABLE_CONTROL1, 0x00000000 },
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{ MT_TX0_RF_GAIN_CORR, 0x003b0005 },
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{ MT_TX0_RF_GAIN_ATTEN, 0x00006900 },
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{ MT_TX0_BB_GAIN_ATTEN, 0x00000400 },
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{ MT_TX_ALC_VGA3, 0x00060006 },
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{ MT_TX_SW_CFG0, 0x00000402 },
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{ MT_TX_SW_CFG1, 0x00000000 },
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{ MT_TX_SW_CFG2, 0x00000000 },
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{ MT_HEADER_TRANS_CTRL_REG, 0x00000000 },
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{ MT_FCE_CSO, 0x0000030f },
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{ MT_FCE_PARAMETERS, 0x00256f0f },
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};
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#endif
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