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https://github.com/AuxXxilium/linux_dsm_epyc7002.git
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889c2b7ec4
Initially, the meson clock directory only hosted 2 controllers drivers, for meson8 and gxbb. At the time, both used the same set of clock drivers so managing the dependencies was not a big concern. Since this ancient time, entropy did its job, controllers with different requirement and specific clock drivers have been added. Unfortunately, we did not do a great job at managing the dependencies between the controllers and the different clock drivers. Some drivers, such as clk-phase or vid-pll-div, are compiled even if they are useless on the target (meson8). As we are adding new controllers, we need to be able to pick a driver w/o pulling the whole thing. The patch aims to clean things up by: * providing a dedicated CONFIG_ for each clock drivers * allowing clock drivers to be compiled as a modules, if possible * stating explicitly which drivers are required by each controller. Signed-off-by: Jerome Brunet <jbrunet@baylibre.com> Signed-off-by: Neil Armstrong <narmstrong@baylibre.com> Link: https://lkml.kernel.org/r/20190201125841.26785-5-jbrunet@baylibre.com
252 lines
5.9 KiB
C
252 lines
5.9 KiB
C
// SPDX-License-Identifier: (GPL-2.0 OR MIT)
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/*
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* Copyright (c) 2018 BayLibre, SAS.
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* Author: Jerome Brunet <jbrunet@baylibre.com>
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*
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* Sample clock generator divider:
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* This HW divider gates with value 0 but is otherwise a zero based divider:
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*
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* val >= 1
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* divider = val + 1
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*
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* The duty cycle may also be set for the LR clock variant. The duty cycle
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* ratio is:
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*
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* hi = [0 - val]
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* duty_cycle = (1 + hi) / (1 + val)
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*/
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#include <linux/clk-provider.h>
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#include <linux/module.h>
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#include "clk-regmap.h"
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#include "sclk-div.h"
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static inline struct meson_sclk_div_data *
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meson_sclk_div_data(struct clk_regmap *clk)
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{
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return (struct meson_sclk_div_data *)clk->data;
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}
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static int sclk_div_maxval(struct meson_sclk_div_data *sclk)
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{
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return (1 << sclk->div.width) - 1;
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}
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static int sclk_div_maxdiv(struct meson_sclk_div_data *sclk)
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{
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return sclk_div_maxval(sclk) + 1;
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}
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static int sclk_div_getdiv(struct clk_hw *hw, unsigned long rate,
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unsigned long prate, int maxdiv)
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{
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int div = DIV_ROUND_CLOSEST_ULL((u64)prate, rate);
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return clamp(div, 2, maxdiv);
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}
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static int sclk_div_bestdiv(struct clk_hw *hw, unsigned long rate,
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unsigned long *prate,
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struct meson_sclk_div_data *sclk)
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{
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struct clk_hw *parent = clk_hw_get_parent(hw);
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int bestdiv = 0, i;
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unsigned long maxdiv, now, parent_now;
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unsigned long best = 0, best_parent = 0;
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if (!rate)
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rate = 1;
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maxdiv = sclk_div_maxdiv(sclk);
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if (!(clk_hw_get_flags(hw) & CLK_SET_RATE_PARENT))
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return sclk_div_getdiv(hw, rate, *prate, maxdiv);
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/*
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* The maximum divider we can use without overflowing
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* unsigned long in rate * i below
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*/
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maxdiv = min(ULONG_MAX / rate, maxdiv);
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for (i = 2; i <= maxdiv; i++) {
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/*
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* It's the most ideal case if the requested rate can be
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* divided from parent clock without needing to change
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* parent rate, so return the divider immediately.
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*/
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if (rate * i == *prate)
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return i;
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parent_now = clk_hw_round_rate(parent, rate * i);
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now = DIV_ROUND_UP_ULL((u64)parent_now, i);
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if (abs(rate - now) < abs(rate - best)) {
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bestdiv = i;
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best = now;
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best_parent = parent_now;
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}
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}
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if (!bestdiv)
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bestdiv = sclk_div_maxdiv(sclk);
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else
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*prate = best_parent;
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return bestdiv;
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}
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static long sclk_div_round_rate(struct clk_hw *hw, unsigned long rate,
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unsigned long *prate)
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{
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struct clk_regmap *clk = to_clk_regmap(hw);
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struct meson_sclk_div_data *sclk = meson_sclk_div_data(clk);
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int div;
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div = sclk_div_bestdiv(hw, rate, prate, sclk);
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return DIV_ROUND_UP_ULL((u64)*prate, div);
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}
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static void sclk_apply_ratio(struct clk_regmap *clk,
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struct meson_sclk_div_data *sclk)
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{
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unsigned int hi = DIV_ROUND_CLOSEST(sclk->cached_div *
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sclk->cached_duty.num,
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sclk->cached_duty.den);
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if (hi)
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hi -= 1;
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meson_parm_write(clk->map, &sclk->hi, hi);
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}
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static int sclk_div_set_duty_cycle(struct clk_hw *hw,
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struct clk_duty *duty)
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{
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struct clk_regmap *clk = to_clk_regmap(hw);
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struct meson_sclk_div_data *sclk = meson_sclk_div_data(clk);
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if (MESON_PARM_APPLICABLE(&sclk->hi)) {
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memcpy(&sclk->cached_duty, duty, sizeof(*duty));
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sclk_apply_ratio(clk, sclk);
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}
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return 0;
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}
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static int sclk_div_get_duty_cycle(struct clk_hw *hw,
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struct clk_duty *duty)
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{
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struct clk_regmap *clk = to_clk_regmap(hw);
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struct meson_sclk_div_data *sclk = meson_sclk_div_data(clk);
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int hi;
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if (!MESON_PARM_APPLICABLE(&sclk->hi)) {
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duty->num = 1;
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duty->den = 2;
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return 0;
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}
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hi = meson_parm_read(clk->map, &sclk->hi);
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duty->num = hi + 1;
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duty->den = sclk->cached_div;
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return 0;
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}
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static void sclk_apply_divider(struct clk_regmap *clk,
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struct meson_sclk_div_data *sclk)
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{
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if (MESON_PARM_APPLICABLE(&sclk->hi))
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sclk_apply_ratio(clk, sclk);
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meson_parm_write(clk->map, &sclk->div, sclk->cached_div - 1);
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}
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static int sclk_div_set_rate(struct clk_hw *hw, unsigned long rate,
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unsigned long prate)
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{
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struct clk_regmap *clk = to_clk_regmap(hw);
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struct meson_sclk_div_data *sclk = meson_sclk_div_data(clk);
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unsigned long maxdiv = sclk_div_maxdiv(sclk);
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sclk->cached_div = sclk_div_getdiv(hw, rate, prate, maxdiv);
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if (clk_hw_is_enabled(hw))
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sclk_apply_divider(clk, sclk);
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return 0;
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}
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static unsigned long sclk_div_recalc_rate(struct clk_hw *hw,
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unsigned long prate)
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{
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struct clk_regmap *clk = to_clk_regmap(hw);
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struct meson_sclk_div_data *sclk = meson_sclk_div_data(clk);
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return DIV_ROUND_UP_ULL((u64)prate, sclk->cached_div);
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}
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static int sclk_div_enable(struct clk_hw *hw)
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{
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struct clk_regmap *clk = to_clk_regmap(hw);
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struct meson_sclk_div_data *sclk = meson_sclk_div_data(clk);
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sclk_apply_divider(clk, sclk);
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return 0;
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}
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static void sclk_div_disable(struct clk_hw *hw)
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{
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struct clk_regmap *clk = to_clk_regmap(hw);
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struct meson_sclk_div_data *sclk = meson_sclk_div_data(clk);
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meson_parm_write(clk->map, &sclk->div, 0);
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}
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static int sclk_div_is_enabled(struct clk_hw *hw)
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{
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struct clk_regmap *clk = to_clk_regmap(hw);
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struct meson_sclk_div_data *sclk = meson_sclk_div_data(clk);
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if (meson_parm_read(clk->map, &sclk->div))
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return 1;
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return 0;
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}
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static void sclk_div_init(struct clk_hw *hw)
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{
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struct clk_regmap *clk = to_clk_regmap(hw);
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struct meson_sclk_div_data *sclk = meson_sclk_div_data(clk);
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unsigned int val;
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val = meson_parm_read(clk->map, &sclk->div);
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/* if the divider is initially disabled, assume max */
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if (!val)
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sclk->cached_div = sclk_div_maxdiv(sclk);
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else
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sclk->cached_div = val + 1;
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sclk_div_get_duty_cycle(hw, &sclk->cached_duty);
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}
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const struct clk_ops meson_sclk_div_ops = {
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.recalc_rate = sclk_div_recalc_rate,
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.round_rate = sclk_div_round_rate,
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.set_rate = sclk_div_set_rate,
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.enable = sclk_div_enable,
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.disable = sclk_div_disable,
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.is_enabled = sclk_div_is_enabled,
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.get_duty_cycle = sclk_div_get_duty_cycle,
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.set_duty_cycle = sclk_div_set_duty_cycle,
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.init = sclk_div_init,
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};
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EXPORT_SYMBOL_GPL(meson_sclk_div_ops);
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MODULE_DESCRIPTION("Amlogic Sample divider driver");
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MODULE_AUTHOR("Jerome Brunet <jbrunet@baylibre.com>");
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MODULE_LICENSE("GPL v2");
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