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4680e64a88
arch/x86/oprofile/op_model_amd.c: In function 'op_amd_handle_ibs': arch/x86/oprofile/op_model_amd.c:217: warning: no return statement in function returning non-void Fix this by making op_amd_handle_ibs() return void. Cc: Robert Richter <robert.richter@amd.com> Signed-off-by: Andrew Morton <akpm@linux-foundation.org> Signed-off-by: Robert Richter <robert.richter@amd.com>
541 lines
12 KiB
C
541 lines
12 KiB
C
/*
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* @file op_model_amd.c
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* athlon / K7 / K8 / Family 10h model-specific MSR operations
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*
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* @remark Copyright 2002-2009 OProfile authors
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* @remark Read the file COPYING
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*
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* @author John Levon
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* @author Philippe Elie
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* @author Graydon Hoare
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* @author Robert Richter <robert.richter@amd.com>
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* @author Barry Kasindorf <barry.kasindorf@amd.com>
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* @author Jason Yeh <jason.yeh@amd.com>
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* @author Suravee Suthikulpanit <suravee.suthikulpanit@amd.com>
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*/
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#include <linux/oprofile.h>
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#include <linux/device.h>
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#include <linux/pci.h>
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#include <linux/percpu.h>
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#include <asm/ptrace.h>
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#include <asm/msr.h>
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#include <asm/nmi.h>
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#include "op_x86_model.h"
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#include "op_counter.h"
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#define NUM_COUNTERS 4
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#define NUM_CONTROLS 4
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#ifdef CONFIG_OPROFILE_EVENT_MULTIPLEX
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#define NUM_VIRT_COUNTERS 32
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#define NUM_VIRT_CONTROLS 32
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#else
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#define NUM_VIRT_COUNTERS NUM_COUNTERS
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#define NUM_VIRT_CONTROLS NUM_CONTROLS
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#endif
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#define OP_EVENT_MASK 0x0FFF
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#define OP_CTR_OVERFLOW (1ULL<<31)
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#define MSR_AMD_EVENTSEL_RESERVED ((0xFFFFFCF0ULL<<32)|(1ULL<<21))
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static unsigned long reset_value[NUM_VIRT_COUNTERS];
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#ifdef CONFIG_OPROFILE_IBS
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/* IbsFetchCtl bits/masks */
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#define IBS_FETCH_RAND_EN (1ULL<<57)
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#define IBS_FETCH_VAL (1ULL<<49)
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#define IBS_FETCH_ENABLE (1ULL<<48)
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#define IBS_FETCH_CNT_MASK 0xFFFF0000ULL
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/*IbsOpCtl bits */
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#define IBS_OP_CNT_CTL (1ULL<<19)
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#define IBS_OP_VAL (1ULL<<18)
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#define IBS_OP_ENABLE (1ULL<<17)
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#define IBS_FETCH_SIZE 6
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#define IBS_OP_SIZE 12
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static int has_ibs; /* AMD Family10h and later */
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struct op_ibs_config {
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unsigned long op_enabled;
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unsigned long fetch_enabled;
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unsigned long max_cnt_fetch;
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unsigned long max_cnt_op;
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unsigned long rand_en;
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unsigned long dispatched_ops;
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};
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static struct op_ibs_config ibs_config;
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#endif
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#ifdef CONFIG_OPROFILE_EVENT_MULTIPLEX
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static void op_mux_fill_in_addresses(struct op_msrs * const msrs)
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{
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int i;
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for (i = 0; i < NUM_VIRT_COUNTERS; i++) {
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int hw_counter = op_x86_virt_to_phys(i);
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if (reserve_perfctr_nmi(MSR_K7_PERFCTR0 + i))
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msrs->multiplex[i].addr = MSR_K7_PERFCTR0 + hw_counter;
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else
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msrs->multiplex[i].addr = 0;
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}
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}
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static void op_mux_switch_ctrl(struct op_x86_model_spec const *model,
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struct op_msrs const * const msrs)
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{
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u64 val;
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int i;
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/* enable active counters */
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for (i = 0; i < NUM_COUNTERS; ++i) {
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int virt = op_x86_phys_to_virt(i);
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if (!counter_config[virt].enabled)
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continue;
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rdmsrl(msrs->controls[i].addr, val);
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val &= model->reserved;
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val |= op_x86_get_ctrl(model, &counter_config[virt]);
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wrmsrl(msrs->controls[i].addr, val);
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}
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}
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#else
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static inline void op_mux_fill_in_addresses(struct op_msrs * const msrs) { }
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#endif
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/* functions for op_amd_spec */
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static void op_amd_fill_in_addresses(struct op_msrs * const msrs)
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{
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int i;
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for (i = 0; i < NUM_COUNTERS; i++) {
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if (reserve_perfctr_nmi(MSR_K7_PERFCTR0 + i))
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msrs->counters[i].addr = MSR_K7_PERFCTR0 + i;
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else
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msrs->counters[i].addr = 0;
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}
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for (i = 0; i < NUM_CONTROLS; i++) {
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if (reserve_evntsel_nmi(MSR_K7_EVNTSEL0 + i))
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msrs->controls[i].addr = MSR_K7_EVNTSEL0 + i;
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else
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msrs->controls[i].addr = 0;
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}
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op_mux_fill_in_addresses(msrs);
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}
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static void op_amd_setup_ctrs(struct op_x86_model_spec const *model,
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struct op_msrs const * const msrs)
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{
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u64 val;
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int i;
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/* setup reset_value */
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for (i = 0; i < NUM_VIRT_COUNTERS; ++i) {
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if (counter_config[i].enabled)
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reset_value[i] = counter_config[i].count;
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else
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reset_value[i] = 0;
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}
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/* clear all counters */
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for (i = 0; i < NUM_CONTROLS; ++i) {
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if (unlikely(!msrs->controls[i].addr))
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continue;
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rdmsrl(msrs->controls[i].addr, val);
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val &= model->reserved;
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wrmsrl(msrs->controls[i].addr, val);
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}
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/* avoid a false detection of ctr overflows in NMI handler */
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for (i = 0; i < NUM_COUNTERS; ++i) {
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if (unlikely(!msrs->counters[i].addr))
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continue;
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wrmsrl(msrs->counters[i].addr, -1LL);
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}
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/* enable active counters */
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for (i = 0; i < NUM_COUNTERS; ++i) {
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int virt = op_x86_phys_to_virt(i);
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if (!counter_config[virt].enabled)
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continue;
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if (!msrs->counters[i].addr)
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continue;
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/* setup counter registers */
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wrmsrl(msrs->counters[i].addr, -(u64)reset_value[virt]);
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/* setup control registers */
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rdmsrl(msrs->controls[i].addr, val);
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val &= model->reserved;
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val |= op_x86_get_ctrl(model, &counter_config[virt]);
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wrmsrl(msrs->controls[i].addr, val);
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}
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}
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#ifdef CONFIG_OPROFILE_IBS
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static inline void
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op_amd_handle_ibs(struct pt_regs * const regs,
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struct op_msrs const * const msrs)
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{
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u64 val, ctl;
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struct op_entry entry;
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if (!has_ibs)
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return;
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if (ibs_config.fetch_enabled) {
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rdmsrl(MSR_AMD64_IBSFETCHCTL, ctl);
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if (ctl & IBS_FETCH_VAL) {
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rdmsrl(MSR_AMD64_IBSFETCHLINAD, val);
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oprofile_write_reserve(&entry, regs, val,
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IBS_FETCH_CODE, IBS_FETCH_SIZE);
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oprofile_add_data64(&entry, val);
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oprofile_add_data64(&entry, ctl);
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rdmsrl(MSR_AMD64_IBSFETCHPHYSAD, val);
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oprofile_add_data64(&entry, val);
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oprofile_write_commit(&entry);
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/* reenable the IRQ */
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ctl &= ~(IBS_FETCH_VAL | IBS_FETCH_CNT_MASK);
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ctl |= IBS_FETCH_ENABLE;
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wrmsrl(MSR_AMD64_IBSFETCHCTL, ctl);
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}
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}
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if (ibs_config.op_enabled) {
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rdmsrl(MSR_AMD64_IBSOPCTL, ctl);
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if (ctl & IBS_OP_VAL) {
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rdmsrl(MSR_AMD64_IBSOPRIP, val);
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oprofile_write_reserve(&entry, regs, val,
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IBS_OP_CODE, IBS_OP_SIZE);
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oprofile_add_data64(&entry, val);
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rdmsrl(MSR_AMD64_IBSOPDATA, val);
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oprofile_add_data64(&entry, val);
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rdmsrl(MSR_AMD64_IBSOPDATA2, val);
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oprofile_add_data64(&entry, val);
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rdmsrl(MSR_AMD64_IBSOPDATA3, val);
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oprofile_add_data64(&entry, val);
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rdmsrl(MSR_AMD64_IBSDCLINAD, val);
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oprofile_add_data64(&entry, val);
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rdmsrl(MSR_AMD64_IBSDCPHYSAD, val);
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oprofile_add_data64(&entry, val);
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oprofile_write_commit(&entry);
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/* reenable the IRQ */
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ctl &= ~IBS_OP_VAL & 0xFFFFFFFF;
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ctl |= IBS_OP_ENABLE;
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wrmsrl(MSR_AMD64_IBSOPCTL, ctl);
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}
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}
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}
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static inline void op_amd_start_ibs(void)
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{
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u64 val;
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if (has_ibs && ibs_config.fetch_enabled) {
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val = (ibs_config.max_cnt_fetch >> 4) & 0xFFFF;
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val |= ibs_config.rand_en ? IBS_FETCH_RAND_EN : 0;
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val |= IBS_FETCH_ENABLE;
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wrmsrl(MSR_AMD64_IBSFETCHCTL, val);
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}
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if (has_ibs && ibs_config.op_enabled) {
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val = (ibs_config.max_cnt_op >> 4) & 0xFFFF;
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val |= ibs_config.dispatched_ops ? IBS_OP_CNT_CTL : 0;
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val |= IBS_OP_ENABLE;
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wrmsrl(MSR_AMD64_IBSOPCTL, val);
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}
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}
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static void op_amd_stop_ibs(void)
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{
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if (has_ibs && ibs_config.fetch_enabled)
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/* clear max count and enable */
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wrmsrl(MSR_AMD64_IBSFETCHCTL, 0);
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if (has_ibs && ibs_config.op_enabled)
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/* clear max count and enable */
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wrmsrl(MSR_AMD64_IBSOPCTL, 0);
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}
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#else
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static inline void op_amd_handle_ibs(struct pt_regs * const regs,
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struct op_msrs const * const msrs) { }
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static inline void op_amd_start_ibs(void) { }
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static inline void op_amd_stop_ibs(void) { }
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#endif
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static int op_amd_check_ctrs(struct pt_regs * const regs,
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struct op_msrs const * const msrs)
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{
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u64 val;
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int i;
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for (i = 0; i < NUM_COUNTERS; ++i) {
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int virt = op_x86_phys_to_virt(i);
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if (!reset_value[virt])
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continue;
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rdmsrl(msrs->counters[i].addr, val);
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/* bit is clear if overflowed: */
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if (val & OP_CTR_OVERFLOW)
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continue;
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oprofile_add_sample(regs, virt);
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wrmsrl(msrs->counters[i].addr, -(u64)reset_value[virt]);
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}
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op_amd_handle_ibs(regs, msrs);
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/* See op_model_ppro.c */
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return 1;
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}
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static void op_amd_start(struct op_msrs const * const msrs)
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{
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u64 val;
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int i;
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for (i = 0; i < NUM_COUNTERS; ++i) {
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if (!reset_value[op_x86_phys_to_virt(i)])
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continue;
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rdmsrl(msrs->controls[i].addr, val);
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val |= ARCH_PERFMON_EVENTSEL0_ENABLE;
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wrmsrl(msrs->controls[i].addr, val);
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}
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op_amd_start_ibs();
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}
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static void op_amd_stop(struct op_msrs const * const msrs)
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{
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u64 val;
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int i;
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/*
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* Subtle: stop on all counters to avoid race with setting our
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* pm callback
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*/
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for (i = 0; i < NUM_COUNTERS; ++i) {
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if (!reset_value[op_x86_phys_to_virt(i)])
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continue;
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rdmsrl(msrs->controls[i].addr, val);
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val &= ~ARCH_PERFMON_EVENTSEL0_ENABLE;
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wrmsrl(msrs->controls[i].addr, val);
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}
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op_amd_stop_ibs();
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}
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static void op_amd_shutdown(struct op_msrs const * const msrs)
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{
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int i;
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for (i = 0; i < NUM_COUNTERS; ++i) {
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if (msrs->counters[i].addr)
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release_perfctr_nmi(MSR_K7_PERFCTR0 + i);
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}
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for (i = 0; i < NUM_CONTROLS; ++i) {
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if (msrs->controls[i].addr)
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release_evntsel_nmi(MSR_K7_EVNTSEL0 + i);
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}
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}
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#ifdef CONFIG_OPROFILE_IBS
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static u8 ibs_eilvt_off;
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static inline void apic_init_ibs_nmi_per_cpu(void *arg)
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{
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ibs_eilvt_off = setup_APIC_eilvt_ibs(0, APIC_EILVT_MSG_NMI, 0);
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}
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static inline void apic_clear_ibs_nmi_per_cpu(void *arg)
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{
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setup_APIC_eilvt_ibs(0, APIC_EILVT_MSG_FIX, 1);
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}
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static int init_ibs_nmi(void)
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{
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#define IBSCTL_LVTOFFSETVAL (1 << 8)
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#define IBSCTL 0x1cc
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struct pci_dev *cpu_cfg;
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int nodes;
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u32 value = 0;
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/* per CPU setup */
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on_each_cpu(apic_init_ibs_nmi_per_cpu, NULL, 1);
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nodes = 0;
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cpu_cfg = NULL;
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do {
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cpu_cfg = pci_get_device(PCI_VENDOR_ID_AMD,
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PCI_DEVICE_ID_AMD_10H_NB_MISC,
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cpu_cfg);
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if (!cpu_cfg)
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break;
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++nodes;
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pci_write_config_dword(cpu_cfg, IBSCTL, ibs_eilvt_off
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| IBSCTL_LVTOFFSETVAL);
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pci_read_config_dword(cpu_cfg, IBSCTL, &value);
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if (value != (ibs_eilvt_off | IBSCTL_LVTOFFSETVAL)) {
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pci_dev_put(cpu_cfg);
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printk(KERN_DEBUG "Failed to setup IBS LVT offset, "
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"IBSCTL = 0x%08x", value);
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return 1;
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}
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} while (1);
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if (!nodes) {
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printk(KERN_DEBUG "No CPU node configured for IBS");
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return 1;
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}
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#ifdef CONFIG_NUMA
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/* Sanity check */
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/* Works only for 64bit with proper numa implementation. */
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if (nodes != num_possible_nodes()) {
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printk(KERN_DEBUG "Failed to setup CPU node(s) for IBS, "
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"found: %d, expected %d",
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nodes, num_possible_nodes());
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return 1;
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}
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#endif
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return 0;
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}
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/* uninitialize the APIC for the IBS interrupts if needed */
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static void clear_ibs_nmi(void)
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{
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if (has_ibs)
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on_each_cpu(apic_clear_ibs_nmi_per_cpu, NULL, 1);
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}
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/* initialize the APIC for the IBS interrupts if available */
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static void ibs_init(void)
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{
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has_ibs = boot_cpu_has(X86_FEATURE_IBS);
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if (!has_ibs)
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return;
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if (init_ibs_nmi()) {
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has_ibs = 0;
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return;
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}
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printk(KERN_INFO "oprofile: AMD IBS detected\n");
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}
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static void ibs_exit(void)
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{
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if (!has_ibs)
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return;
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clear_ibs_nmi();
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}
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static int (*create_arch_files)(struct super_block *sb, struct dentry *root);
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static int setup_ibs_files(struct super_block *sb, struct dentry *root)
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{
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struct dentry *dir;
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int ret = 0;
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/* architecture specific files */
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if (create_arch_files)
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ret = create_arch_files(sb, root);
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if (ret)
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return ret;
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|
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if (!has_ibs)
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return ret;
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|
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/* model specific files */
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/* setup some reasonable defaults */
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ibs_config.max_cnt_fetch = 250000;
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ibs_config.fetch_enabled = 0;
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ibs_config.max_cnt_op = 250000;
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ibs_config.op_enabled = 0;
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ibs_config.dispatched_ops = 1;
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dir = oprofilefs_mkdir(sb, root, "ibs_fetch");
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oprofilefs_create_ulong(sb, dir, "enable",
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&ibs_config.fetch_enabled);
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oprofilefs_create_ulong(sb, dir, "max_count",
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&ibs_config.max_cnt_fetch);
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oprofilefs_create_ulong(sb, dir, "rand_enable",
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&ibs_config.rand_en);
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dir = oprofilefs_mkdir(sb, root, "ibs_op");
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oprofilefs_create_ulong(sb, dir, "enable",
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&ibs_config.op_enabled);
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oprofilefs_create_ulong(sb, dir, "max_count",
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&ibs_config.max_cnt_op);
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oprofilefs_create_ulong(sb, dir, "dispatched_ops",
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&ibs_config.dispatched_ops);
|
|
|
|
return 0;
|
|
}
|
|
|
|
static int op_amd_init(struct oprofile_operations *ops)
|
|
{
|
|
ibs_init();
|
|
create_arch_files = ops->create_files;
|
|
ops->create_files = setup_ibs_files;
|
|
return 0;
|
|
}
|
|
|
|
static void op_amd_exit(void)
|
|
{
|
|
ibs_exit();
|
|
}
|
|
|
|
#else
|
|
|
|
/* no IBS support */
|
|
|
|
static int op_amd_init(struct oprofile_operations *ops)
|
|
{
|
|
return 0;
|
|
}
|
|
|
|
static void op_amd_exit(void) {}
|
|
|
|
#endif /* CONFIG_OPROFILE_IBS */
|
|
|
|
struct op_x86_model_spec op_amd_spec = {
|
|
.num_counters = NUM_COUNTERS,
|
|
.num_controls = NUM_CONTROLS,
|
|
.num_virt_counters = NUM_VIRT_COUNTERS,
|
|
.reserved = MSR_AMD_EVENTSEL_RESERVED,
|
|
.event_mask = OP_EVENT_MASK,
|
|
.init = op_amd_init,
|
|
.exit = op_amd_exit,
|
|
.fill_in_addresses = &op_amd_fill_in_addresses,
|
|
.setup_ctrs = &op_amd_setup_ctrs,
|
|
.check_ctrs = &op_amd_check_ctrs,
|
|
.start = &op_amd_start,
|
|
.stop = &op_amd_stop,
|
|
.shutdown = &op_amd_shutdown,
|
|
#ifdef CONFIG_OPROFILE_EVENT_MULTIPLEX
|
|
.switch_ctrl = &op_mux_switch_ctrl,
|
|
#endif
|
|
};
|