Tony Luck 45bc6098a3 EDAC/{i7core,sb,pnd2,skx}: Fix error event severity ... IA32_MCG_STATUS.RIPV indicates whether the return RIP value pushed onto the stack as part of machine check delivery is valid or not. Various drivers copied a code fragment that uses the RIPV bit to determine the severity of the error as either HW_EVENT_ERR_UNCORRECTED or HW_EVENT_ERR_FATAL, but this check is reversed (marking errors where RIPV is set as "FATAL"). Reverse the tests so that the error is marked fatal when RIPV is not set. Reported-by: Gabriele Paoloni <gabriele.paoloni@intel.com> Signed-off-by: Tony Luck <tony.luck@intel.com> Signed-off-by: Borislav Petkov <bp@suse.de> Cc: <stable@vger.kernel.org> Link: https://lkml.kernel.org/r/20200707194324.14884-1-tony.luck@intel.com		2020-08-18 15:40:30 +02:00
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altera_edac.c
altera_edac.h
amd64_edac_dbg.c
amd64_edac_inj.c
amd64_edac.c
amd64_edac.h
amd76x_edac.c
amd8111_edac.c
amd8111_edac.h
amd8131_edac.c
amd8131_edac.h
armada_xp_edac.c
aspeed_edac.c
bluefield_edac.c
cell_edac.c
cpc925_edac.c
debugfs.c
dmc520_edac.c
e7xxx_edac.c
e752x_edac.c
edac_device_sysfs.c
edac_device.c
edac_device.h
edac_mc_sysfs.c
edac_mc.c
edac_mc.h
edac_module.c
edac_module.h
edac_pci_sysfs.c
edac_pci.c
edac_pci.h
fsl_ddr_edac.c
fsl_ddr_edac.h
ghes_edac.c
highbank_l2_edac.c
highbank_mc_edac.c
i7core_edac.c
i10nm_base.c
i3000_edac.c
i3200_edac.c
i5000_edac.c
i5100_edac.c
i5400_edac.c
i7300_edac.c
i82443bxgx_edac.c
i82860_edac.c
i82875p_edac.c
i82975x_edac.c
ie31200_edac.c
Kconfig
layerscape_edac.c
Makefile
mce_amd.c
mce_amd.h
mpc85xx_edac.c
mpc85xx_edac.h
mv64x60_edac.c
mv64x60_edac.h
octeon_edac-l2c.c
octeon_edac-lmc.c
octeon_edac-pc.c
octeon_edac-pci.c
pasemi_edac.c
pnd2_edac.c
pnd2_edac.h
ppc4xx_edac.c
ppc4xx_edac.h
qcom_edac.c
r82600_edac.c
sb_edac.c
sifive_edac.c
skx_base.c
skx_common.c
skx_common.h
synopsys_edac.c
thunderx_edac.c
ti_edac.c
wq.c
x38_edac.c
xgene_edac.c