mirror of
https://github.com/AuxXxilium/linux_dsm_epyc7002.git
synced 2024-12-26 18:35:26 +07:00
b11cfaba5b
During probe, bypass clocks (i.e. ee-in-xtal) are made from device-tree inputs to provide input clocks which can be access through global name. The cons of this method are the duplicated clocks, means more string comparison. Specify parent directly with device-tree clock name. Remove the bypass clock registration from the ee probe function. Signed-off-by: Alexandre Mergnat <amergnat@baylibre.com> Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
108 lines
2.7 KiB
Plaintext
108 lines
2.7 KiB
Plaintext
# SPDX-License-Identifier: GPL-2.0-only
|
|
config COMMON_CLK_MESON_INPUT
|
|
tristate
|
|
|
|
config COMMON_CLK_MESON_REGMAP
|
|
tristate
|
|
select REGMAP
|
|
|
|
config COMMON_CLK_MESON_DUALDIV
|
|
tristate
|
|
select COMMON_CLK_MESON_REGMAP
|
|
|
|
config COMMON_CLK_MESON_MPLL
|
|
tristate
|
|
select COMMON_CLK_MESON_REGMAP
|
|
|
|
config COMMON_CLK_MESON_PHASE
|
|
tristate
|
|
select COMMON_CLK_MESON_REGMAP
|
|
|
|
config COMMON_CLK_MESON_PLL
|
|
tristate
|
|
select COMMON_CLK_MESON_REGMAP
|
|
|
|
config COMMON_CLK_MESON_SCLK_DIV
|
|
tristate
|
|
select COMMON_CLK_MESON_REGMAP
|
|
|
|
config COMMON_CLK_MESON_VID_PLL_DIV
|
|
tristate
|
|
select COMMON_CLK_MESON_REGMAP
|
|
|
|
config COMMON_CLK_MESON_AO_CLKC
|
|
tristate
|
|
select COMMON_CLK_MESON_REGMAP
|
|
select RESET_CONTROLLER
|
|
|
|
config COMMON_CLK_MESON_EE_CLKC
|
|
tristate
|
|
select COMMON_CLK_MESON_REGMAP
|
|
|
|
config COMMON_CLK_MESON8B
|
|
bool
|
|
depends on ARCH_MESON
|
|
select COMMON_CLK_MESON_REGMAP
|
|
select COMMON_CLK_MESON_MPLL
|
|
select COMMON_CLK_MESON_PLL
|
|
select MFD_SYSCON
|
|
select RESET_CONTROLLER
|
|
help
|
|
Support for the clock controller on AmLogic S802 (Meson8),
|
|
S805 (Meson8b) and S812 (Meson8m2) devices. Say Y if you
|
|
want peripherals and CPU frequency scaling to work.
|
|
|
|
config COMMON_CLK_GXBB
|
|
bool
|
|
depends on ARCH_MESON
|
|
select COMMON_CLK_MESON_REGMAP
|
|
select COMMON_CLK_MESON_DUALDIV
|
|
select COMMON_CLK_MESON_VID_PLL_DIV
|
|
select COMMON_CLK_MESON_MPLL
|
|
select COMMON_CLK_MESON_PLL
|
|
select COMMON_CLK_MESON_AO_CLKC
|
|
select COMMON_CLK_MESON_EE_CLKC
|
|
select MFD_SYSCON
|
|
help
|
|
Support for the clock controller on AmLogic S905 devices, aka gxbb.
|
|
Say Y if you want peripherals and CPU frequency scaling to work.
|
|
|
|
config COMMON_CLK_AXG
|
|
bool
|
|
depends on ARCH_MESON
|
|
select COMMON_CLK_MESON_REGMAP
|
|
select COMMON_CLK_MESON_DUALDIV
|
|
select COMMON_CLK_MESON_MPLL
|
|
select COMMON_CLK_MESON_PLL
|
|
select COMMON_CLK_MESON_AO_CLKC
|
|
select COMMON_CLK_MESON_EE_CLKC
|
|
select MFD_SYSCON
|
|
help
|
|
Support for the clock controller on AmLogic A113D devices, aka axg.
|
|
Say Y if you want peripherals and CPU frequency scaling to work.
|
|
|
|
config COMMON_CLK_AXG_AUDIO
|
|
tristate "Meson AXG Audio Clock Controller Driver"
|
|
depends on ARCH_MESON
|
|
select COMMON_CLK_MESON_REGMAP
|
|
select COMMON_CLK_MESON_PHASE
|
|
select COMMON_CLK_MESON_SCLK_DIV
|
|
select REGMAP_MMIO
|
|
help
|
|
Support for the audio clock controller on AmLogic A113D devices,
|
|
aka axg, Say Y if you want audio subsystem to work.
|
|
|
|
config COMMON_CLK_G12A
|
|
bool
|
|
depends on ARCH_MESON
|
|
select COMMON_CLK_MESON_REGMAP
|
|
select COMMON_CLK_MESON_DUALDIV
|
|
select COMMON_CLK_MESON_MPLL
|
|
select COMMON_CLK_MESON_PLL
|
|
select COMMON_CLK_MESON_AO_CLKC
|
|
select COMMON_CLK_MESON_EE_CLKC
|
|
select MFD_SYSCON
|
|
help
|
|
Support for the clock controller on Amlogic S905D2, S905X2 and S905Y2
|
|
devices, aka g12a. Say Y if you want peripherals to work.
|