mirror of
https://github.com/AuxXxilium/linux_dsm_epyc7002.git
synced 2024-12-25 02:18:23 +07:00
b0df0b251b
Backmerge Linus master to get the connector locking revert. * 'master' of git://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux: (645 commits) sysctl: fix proc_doulongvec_ms_jiffies_minmax() Revert "drm/probe-helpers: Drop locking from poll_enable" MAINTAINERS: add Dan Streetman to zbud maintainers MAINTAINERS: add Dan Streetman to zswap maintainers mm: do not export ioremap_page_range symbol for external module mn10300: fix build error of missing fpu_save() romfs: use different way to generate fsid for BLOCK or MTD frv: add missing atomic64 operations mm, page_alloc: fix premature OOM when racing with cpuset mems update mm, page_alloc: move cpuset seqcount checking to slowpath mm, page_alloc: fix fast-path race with cpuset update or removal mm, page_alloc: fix check for NULL preferred_zone kernel/panic.c: add missing \n fbdev: color map copying bounds checking frv: add atomic64_add_unless() mm/mempolicy.c: do not put mempolicy before using its nodemask radix-tree: fix private list warnings Documentation/filesystems/proc.txt: add VmPin mm, memcg: do not retry precharge charges proc: add a schedule point in proc_pid_readdir() ...
576 lines
15 KiB
C
576 lines
15 KiB
C
/*
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* Copyright(c) 2011-2016 Intel Corporation. All rights reserved.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice (including the next
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* paragraph) shall be included in all copies or substantial portions of the
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* Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
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* SOFTWARE.
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*
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* Authors:
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* Zhi Wang <zhi.a.wang@intel.com>
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*
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* Contributors:
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* Ping Gao <ping.a.gao@intel.com>
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* Tina Zhang <tina.zhang@intel.com>
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* Chanbin Du <changbin.du@intel.com>
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* Min He <min.he@intel.com>
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* Bing Niu <bing.niu@intel.com>
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* Zhenyu Wang <zhenyuw@linux.intel.com>
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*
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*/
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#include <linux/kthread.h>
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#include "i915_drv.h"
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#include "gvt.h"
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#define RING_CTX_OFF(x) \
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offsetof(struct execlist_ring_context, x)
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static void set_context_pdp_root_pointer(
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struct execlist_ring_context *ring_context,
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u32 pdp[8])
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{
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struct execlist_mmio_pair *pdp_pair = &ring_context->pdp3_UDW;
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int i;
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for (i = 0; i < 8; i++)
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pdp_pair[i].val = pdp[7 - i];
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}
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static int populate_shadow_context(struct intel_vgpu_workload *workload)
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{
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struct intel_vgpu *vgpu = workload->vgpu;
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struct intel_gvt *gvt = vgpu->gvt;
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int ring_id = workload->ring_id;
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struct i915_gem_context *shadow_ctx = workload->vgpu->shadow_ctx;
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struct drm_i915_gem_object *ctx_obj =
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shadow_ctx->engine[ring_id].state->obj;
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struct execlist_ring_context *shadow_ring_context;
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struct page *page;
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void *dst;
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unsigned long context_gpa, context_page_num;
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int i;
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gvt_dbg_sched("ring id %d workload lrca %x", ring_id,
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workload->ctx_desc.lrca);
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context_page_num = intel_lr_context_size(
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gvt->dev_priv->engine[ring_id]);
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context_page_num = context_page_num >> PAGE_SHIFT;
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if (IS_BROADWELL(gvt->dev_priv) && ring_id == RCS)
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context_page_num = 19;
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i = 2;
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while (i < context_page_num) {
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context_gpa = intel_vgpu_gma_to_gpa(vgpu->gtt.ggtt_mm,
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(u32)((workload->ctx_desc.lrca + i) <<
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GTT_PAGE_SHIFT));
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if (context_gpa == INTEL_GVT_INVALID_ADDR) {
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gvt_err("Invalid guest context descriptor\n");
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return -EINVAL;
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}
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page = i915_gem_object_get_page(ctx_obj, LRC_PPHWSP_PN + i);
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dst = kmap(page);
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intel_gvt_hypervisor_read_gpa(vgpu, context_gpa, dst,
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GTT_PAGE_SIZE);
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kunmap(page);
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i++;
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}
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page = i915_gem_object_get_page(ctx_obj, LRC_STATE_PN);
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shadow_ring_context = kmap(page);
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#define COPY_REG(name) \
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intel_gvt_hypervisor_read_gpa(vgpu, workload->ring_context_gpa \
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+ RING_CTX_OFF(name.val), &shadow_ring_context->name.val, 4)
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COPY_REG(ctx_ctrl);
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COPY_REG(ctx_timestamp);
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if (ring_id == RCS) {
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COPY_REG(bb_per_ctx_ptr);
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COPY_REG(rcs_indirect_ctx);
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COPY_REG(rcs_indirect_ctx_offset);
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}
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#undef COPY_REG
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set_context_pdp_root_pointer(shadow_ring_context,
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workload->shadow_mm->shadow_page_table);
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intel_gvt_hypervisor_read_gpa(vgpu,
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workload->ring_context_gpa +
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sizeof(*shadow_ring_context),
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(void *)shadow_ring_context +
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sizeof(*shadow_ring_context),
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GTT_PAGE_SIZE - sizeof(*shadow_ring_context));
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kunmap(page);
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return 0;
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}
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static int shadow_context_status_change(struct notifier_block *nb,
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unsigned long action, void *data)
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{
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struct intel_vgpu *vgpu = container_of(nb,
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struct intel_vgpu, shadow_ctx_notifier_block);
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struct drm_i915_gem_request *req =
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(struct drm_i915_gem_request *)data;
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struct intel_gvt_workload_scheduler *scheduler =
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&vgpu->gvt->scheduler;
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struct intel_vgpu_workload *workload =
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scheduler->current_workload[req->engine->id];
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switch (action) {
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case INTEL_CONTEXT_SCHEDULE_IN:
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intel_gvt_load_render_mmio(workload->vgpu,
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workload->ring_id);
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atomic_set(&workload->shadow_ctx_active, 1);
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break;
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case INTEL_CONTEXT_SCHEDULE_OUT:
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intel_gvt_restore_render_mmio(workload->vgpu,
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workload->ring_id);
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atomic_set(&workload->shadow_ctx_active, 0);
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break;
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default:
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WARN_ON(1);
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return NOTIFY_OK;
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}
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wake_up(&workload->shadow_ctx_status_wq);
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return NOTIFY_OK;
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}
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static int dispatch_workload(struct intel_vgpu_workload *workload)
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{
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int ring_id = workload->ring_id;
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struct i915_gem_context *shadow_ctx = workload->vgpu->shadow_ctx;
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struct drm_i915_private *dev_priv = workload->vgpu->gvt->dev_priv;
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struct drm_i915_gem_request *rq;
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int ret;
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gvt_dbg_sched("ring id %d prepare to dispatch workload %p\n",
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ring_id, workload);
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shadow_ctx->desc_template = workload->ctx_desc.addressing_mode <<
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GEN8_CTX_ADDRESSING_MODE_SHIFT;
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mutex_lock(&dev_priv->drm.struct_mutex);
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rq = i915_gem_request_alloc(dev_priv->engine[ring_id], shadow_ctx);
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if (IS_ERR(rq)) {
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gvt_err("fail to allocate gem request\n");
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ret = PTR_ERR(rq);
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goto out;
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}
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gvt_dbg_sched("ring id %d get i915 gem request %p\n", ring_id, rq);
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workload->req = i915_gem_request_get(rq);
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ret = intel_gvt_scan_and_shadow_workload(workload);
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if (ret)
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goto out;
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ret = intel_gvt_scan_and_shadow_wa_ctx(&workload->wa_ctx);
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if (ret)
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goto out;
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ret = populate_shadow_context(workload);
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if (ret)
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goto out;
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if (workload->prepare) {
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ret = workload->prepare(workload);
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if (ret)
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goto out;
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}
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gvt_dbg_sched("ring id %d submit workload to i915 %p\n",
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ring_id, workload->req);
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ret = 0;
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workload->dispatched = true;
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out:
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if (ret)
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workload->status = ret;
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if (!IS_ERR_OR_NULL(rq))
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i915_add_request_no_flush(rq);
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mutex_unlock(&dev_priv->drm.struct_mutex);
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return ret;
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}
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static struct intel_vgpu_workload *pick_next_workload(
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struct intel_gvt *gvt, int ring_id)
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{
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struct intel_gvt_workload_scheduler *scheduler = &gvt->scheduler;
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struct intel_vgpu_workload *workload = NULL;
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mutex_lock(&gvt->lock);
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/*
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* no current vgpu / will be scheduled out / no workload
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* bail out
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*/
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if (!scheduler->current_vgpu) {
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gvt_dbg_sched("ring id %d stop - no current vgpu\n", ring_id);
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goto out;
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}
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if (scheduler->need_reschedule) {
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gvt_dbg_sched("ring id %d stop - will reschedule\n", ring_id);
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goto out;
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}
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if (list_empty(workload_q_head(scheduler->current_vgpu, ring_id))) {
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gvt_dbg_sched("ring id %d stop - no available workload\n",
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ring_id);
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goto out;
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}
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/*
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* still have current workload, maybe the workload disptacher
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* fail to submit it for some reason, resubmit it.
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*/
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if (scheduler->current_workload[ring_id]) {
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workload = scheduler->current_workload[ring_id];
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gvt_dbg_sched("ring id %d still have current workload %p\n",
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ring_id, workload);
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goto out;
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}
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/*
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* pick a workload as current workload
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* once current workload is set, schedule policy routines
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* will wait the current workload is finished when trying to
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* schedule out a vgpu.
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*/
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scheduler->current_workload[ring_id] = container_of(
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workload_q_head(scheduler->current_vgpu, ring_id)->next,
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struct intel_vgpu_workload, list);
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workload = scheduler->current_workload[ring_id];
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gvt_dbg_sched("ring id %d pick new workload %p\n", ring_id, workload);
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atomic_inc(&workload->vgpu->running_workload_num);
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out:
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mutex_unlock(&gvt->lock);
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return workload;
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}
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static void update_guest_context(struct intel_vgpu_workload *workload)
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{
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struct intel_vgpu *vgpu = workload->vgpu;
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struct intel_gvt *gvt = vgpu->gvt;
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int ring_id = workload->ring_id;
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struct i915_gem_context *shadow_ctx = workload->vgpu->shadow_ctx;
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struct drm_i915_gem_object *ctx_obj =
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shadow_ctx->engine[ring_id].state->obj;
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struct execlist_ring_context *shadow_ring_context;
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struct page *page;
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void *src;
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unsigned long context_gpa, context_page_num;
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int i;
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gvt_dbg_sched("ring id %d workload lrca %x\n", ring_id,
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workload->ctx_desc.lrca);
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context_page_num = intel_lr_context_size(
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gvt->dev_priv->engine[ring_id]);
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context_page_num = context_page_num >> PAGE_SHIFT;
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if (IS_BROADWELL(gvt->dev_priv) && ring_id == RCS)
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context_page_num = 19;
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i = 2;
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while (i < context_page_num) {
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context_gpa = intel_vgpu_gma_to_gpa(vgpu->gtt.ggtt_mm,
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(u32)((workload->ctx_desc.lrca + i) <<
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GTT_PAGE_SHIFT));
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if (context_gpa == INTEL_GVT_INVALID_ADDR) {
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gvt_err("invalid guest context descriptor\n");
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return;
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}
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page = i915_gem_object_get_page(ctx_obj, LRC_PPHWSP_PN + i);
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src = kmap(page);
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intel_gvt_hypervisor_write_gpa(vgpu, context_gpa, src,
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GTT_PAGE_SIZE);
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kunmap(page);
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i++;
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}
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intel_gvt_hypervisor_write_gpa(vgpu, workload->ring_context_gpa +
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RING_CTX_OFF(ring_header.val), &workload->rb_tail, 4);
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page = i915_gem_object_get_page(ctx_obj, LRC_STATE_PN);
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shadow_ring_context = kmap(page);
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#define COPY_REG(name) \
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intel_gvt_hypervisor_write_gpa(vgpu, workload->ring_context_gpa + \
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RING_CTX_OFF(name.val), &shadow_ring_context->name.val, 4)
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COPY_REG(ctx_ctrl);
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COPY_REG(ctx_timestamp);
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#undef COPY_REG
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intel_gvt_hypervisor_write_gpa(vgpu,
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workload->ring_context_gpa +
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sizeof(*shadow_ring_context),
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(void *)shadow_ring_context +
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sizeof(*shadow_ring_context),
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GTT_PAGE_SIZE - sizeof(*shadow_ring_context));
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kunmap(page);
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}
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static void complete_current_workload(struct intel_gvt *gvt, int ring_id)
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{
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struct intel_gvt_workload_scheduler *scheduler = &gvt->scheduler;
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struct intel_vgpu_workload *workload;
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struct intel_vgpu *vgpu;
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int event;
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mutex_lock(&gvt->lock);
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workload = scheduler->current_workload[ring_id];
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vgpu = workload->vgpu;
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if (!workload->status && !vgpu->resetting) {
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wait_event(workload->shadow_ctx_status_wq,
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!atomic_read(&workload->shadow_ctx_active));
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update_guest_context(workload);
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for_each_set_bit(event, workload->pending_events,
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INTEL_GVT_EVENT_MAX)
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intel_vgpu_trigger_virtual_event(vgpu, event);
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}
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gvt_dbg_sched("ring id %d complete workload %p status %d\n",
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ring_id, workload, workload->status);
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scheduler->current_workload[ring_id] = NULL;
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list_del_init(&workload->list);
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workload->complete(workload);
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atomic_dec(&vgpu->running_workload_num);
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wake_up(&scheduler->workload_complete_wq);
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mutex_unlock(&gvt->lock);
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}
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struct workload_thread_param {
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struct intel_gvt *gvt;
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int ring_id;
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};
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static DEFINE_MUTEX(scheduler_mutex);
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static int workload_thread(void *priv)
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{
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struct workload_thread_param *p = (struct workload_thread_param *)priv;
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struct intel_gvt *gvt = p->gvt;
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int ring_id = p->ring_id;
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struct intel_gvt_workload_scheduler *scheduler = &gvt->scheduler;
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struct intel_vgpu_workload *workload = NULL;
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long lret;
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int ret;
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bool need_force_wake = IS_SKYLAKE(gvt->dev_priv);
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DEFINE_WAIT_FUNC(wait, woken_wake_function);
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kfree(p);
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gvt_dbg_core("workload thread for ring %d started\n", ring_id);
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while (!kthread_should_stop()) {
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add_wait_queue(&scheduler->waitq[ring_id], &wait);
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do {
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workload = pick_next_workload(gvt, ring_id);
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if (workload)
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break;
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wait_woken(&wait, TASK_INTERRUPTIBLE,
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MAX_SCHEDULE_TIMEOUT);
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} while (!kthread_should_stop());
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remove_wait_queue(&scheduler->waitq[ring_id], &wait);
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if (!workload)
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break;
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mutex_lock(&scheduler_mutex);
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gvt_dbg_sched("ring id %d next workload %p vgpu %d\n",
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workload->ring_id, workload,
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workload->vgpu->id);
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intel_runtime_pm_get(gvt->dev_priv);
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gvt_dbg_sched("ring id %d will dispatch workload %p\n",
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workload->ring_id, workload);
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if (need_force_wake)
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intel_uncore_forcewake_get(gvt->dev_priv,
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FORCEWAKE_ALL);
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mutex_lock(&gvt->lock);
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ret = dispatch_workload(workload);
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mutex_unlock(&gvt->lock);
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if (ret) {
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gvt_err("fail to dispatch workload, skip\n");
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goto complete;
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}
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gvt_dbg_sched("ring id %d wait workload %p\n",
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workload->ring_id, workload);
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lret = i915_wait_request(workload->req,
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0, MAX_SCHEDULE_TIMEOUT);
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if (lret < 0) {
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workload->status = lret;
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gvt_err("fail to wait workload, skip\n");
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} else {
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workload->status = 0;
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}
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complete:
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gvt_dbg_sched("will complete workload %p\n, status: %d\n",
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workload, workload->status);
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if (workload->req)
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i915_gem_request_put(fetch_and_zero(&workload->req));
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complete_current_workload(gvt, ring_id);
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if (need_force_wake)
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intel_uncore_forcewake_put(gvt->dev_priv,
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FORCEWAKE_ALL);
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intel_runtime_pm_put(gvt->dev_priv);
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mutex_unlock(&scheduler_mutex);
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}
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return 0;
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}
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void intel_gvt_wait_vgpu_idle(struct intel_vgpu *vgpu)
|
|
{
|
|
struct intel_gvt *gvt = vgpu->gvt;
|
|
struct intel_gvt_workload_scheduler *scheduler = &gvt->scheduler;
|
|
|
|
if (atomic_read(&vgpu->running_workload_num)) {
|
|
gvt_dbg_sched("wait vgpu idle\n");
|
|
|
|
wait_event(scheduler->workload_complete_wq,
|
|
!atomic_read(&vgpu->running_workload_num));
|
|
}
|
|
}
|
|
|
|
void intel_gvt_clean_workload_scheduler(struct intel_gvt *gvt)
|
|
{
|
|
struct intel_gvt_workload_scheduler *scheduler = &gvt->scheduler;
|
|
int i;
|
|
|
|
gvt_dbg_core("clean workload scheduler\n");
|
|
|
|
for (i = 0; i < I915_NUM_ENGINES; i++) {
|
|
if (scheduler->thread[i]) {
|
|
kthread_stop(scheduler->thread[i]);
|
|
scheduler->thread[i] = NULL;
|
|
}
|
|
}
|
|
}
|
|
|
|
int intel_gvt_init_workload_scheduler(struct intel_gvt *gvt)
|
|
{
|
|
struct intel_gvt_workload_scheduler *scheduler = &gvt->scheduler;
|
|
struct workload_thread_param *param = NULL;
|
|
int ret;
|
|
int i;
|
|
|
|
gvt_dbg_core("init workload scheduler\n");
|
|
|
|
init_waitqueue_head(&scheduler->workload_complete_wq);
|
|
|
|
for (i = 0; i < I915_NUM_ENGINES; i++) {
|
|
/* check ring mask at init time */
|
|
if (!HAS_ENGINE(gvt->dev_priv, i))
|
|
continue;
|
|
|
|
init_waitqueue_head(&scheduler->waitq[i]);
|
|
|
|
param = kzalloc(sizeof(*param), GFP_KERNEL);
|
|
if (!param) {
|
|
ret = -ENOMEM;
|
|
goto err;
|
|
}
|
|
|
|
param->gvt = gvt;
|
|
param->ring_id = i;
|
|
|
|
scheduler->thread[i] = kthread_run(workload_thread, param,
|
|
"gvt workload %d", i);
|
|
if (IS_ERR(scheduler->thread[i])) {
|
|
gvt_err("fail to create workload thread\n");
|
|
ret = PTR_ERR(scheduler->thread[i]);
|
|
goto err;
|
|
}
|
|
}
|
|
return 0;
|
|
err:
|
|
intel_gvt_clean_workload_scheduler(gvt);
|
|
kfree(param);
|
|
param = NULL;
|
|
return ret;
|
|
}
|
|
|
|
void intel_vgpu_clean_gvt_context(struct intel_vgpu *vgpu)
|
|
{
|
|
atomic_notifier_chain_unregister(&vgpu->shadow_ctx->status_notifier,
|
|
&vgpu->shadow_ctx_notifier_block);
|
|
|
|
i915_gem_context_put_unlocked(vgpu->shadow_ctx);
|
|
}
|
|
|
|
int intel_vgpu_init_gvt_context(struct intel_vgpu *vgpu)
|
|
{
|
|
atomic_set(&vgpu->running_workload_num, 0);
|
|
|
|
vgpu->shadow_ctx = i915_gem_context_create_gvt(
|
|
&vgpu->gvt->dev_priv->drm);
|
|
if (IS_ERR(vgpu->shadow_ctx))
|
|
return PTR_ERR(vgpu->shadow_ctx);
|
|
|
|
vgpu->shadow_ctx->engine[RCS].initialised = true;
|
|
|
|
vgpu->shadow_ctx_notifier_block.notifier_call =
|
|
shadow_context_status_change;
|
|
|
|
atomic_notifier_chain_register(&vgpu->shadow_ctx->status_notifier,
|
|
&vgpu->shadow_ctx_notifier_block);
|
|
return 0;
|
|
}
|