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b0b3384612
linux_dsm_epyc7002/drivers/gpu/drm/i915
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Ville Syrjälä b0b3384612 drm/i915: Trick CL2 into life on CHV when using pipe B with port B 
Normmally the common lane in a PHY channel gets powered up when some
of the data lanes get powered up. But when we're driving port B with
pipe B we don't want to enabled any of the data lanes, and just want
the DPLL in the common lane to be active.

To make that happens we have to temporarily enable some data lanes
after which we can access the DPLL registers in the common lane. Once
the pipe is up and running we can drop the power override on the data
lanes allowing them to shut down. From this point forward the common
lane will in fact stay powered on until the data lanes in the other
channel get powered down.

Ville's extended explanation from the review thread:

On Wed, Aug 19, 2015 at 07:47:41AM +0530, Deepak wrote:
> One Q, why only for port B? Port C is also in same common lane right?

Port B is in the first PHY channel which also houses CL1. CL1 always
powers up whenever any lanes in either PHY channel are powered up.
CL2 only powers up if lanes in the second channel (ie. the one with
port C) powers up.

So in this scenario (pipe B->port B) we want the DPLL from CL2, but
ideally we only want to power up the lanes for port B. Powering up
port B lanes will only power up CL1, but as we need CL2 instead we
need to, temporarily, power up some lanes in port C as well.

Crossing the streams the other way (pipe A->port C) is not a problem
since CL1 powers up whenever anything else powers up. So powering up
some port C lanes is enough on its own to make the CL1 DPLL
operational, even though CL1 and the lanes live in separate channels.

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Reviewed-by: Deepak S <deepak.s@linux.intel.com>
[danvet: Amend commit message with extended explanation.]
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
2015-08-26 14:35:06 +02:00
..
dvo_ch7xxx.c
dvo_ch7017.c
dvo_ivch.c Fix resume from suspend on IBM X30 2015-06-15 12:21:01 +02:00
dvo_ns2501.c drm/i915: Enable dithering on NatSemi DVO2501 for Fujitsu S6010 2015-04-23 21:31:58 +02:00
dvo_sil164.c
dvo_tfp410.c
dvo.h
i915_cmd_parser.c drm/i915: Change SRM, LRM instructions to use correct length 2015-08-26 08:44:41 +02:00
i915_debugfs.c drm/i915: Fix some gcc warnings 2015-08-26 11:19:22 +02:00
i915_dma.c drm/i915: Move DPIO port init earlier 2015-08-26 10:22:29 +02:00
i915_drv.c drm/i915/skl: send opregion_nofify_adapter(PCI_D1) instead of PCI_D3 2015-08-05 10:27:41 +02:00
i915_drv.h drm/i915: Store max dotclock 2015-08-26 10:28:54 +02:00
i915_gem_batch_pool.c drm/i915: Split batch pool into size buckets 2015-04-10 08:56:05 +02:00
i915_gem_batch_pool.h drm/i915: Split batch pool into size buckets 2015-04-10 08:56:05 +02:00
i915_gem_context.c drm/i915: Remove the failed context from the fpriv->context_idr 2015-08-14 17:50:41 +02:00
i915_gem_debug.c drm/i915: Implement inter-engine read-read optimisations 2015-05-21 15:11:42 +02:00
i915_gem_dmabuf.c drm/i915: remove unused has_dma_mapping flag 2015-07-13 22:42:41 +02:00
i915_gem_evict.c drm/i915: kerneldoc for i915_gem_shrinker.c 2015-03-20 11:48:16 +01:00
i915_gem_execbuffer.c Merge tag 'drm-intel-fixes-2015-07-15' into drm-intel-next-queued 2015-07-15 16:36:50 +02:00
i915_gem_fence.c drm/i915/gtt: Allow >= 4GB offsets in X86_32 2015-08-14 18:16:30 +02:00
i915_gem_gtt.c drm/i915: Always pass dev pointer in pdp_init 2015-08-14 18:16:31 +02:00
i915_gem_gtt.h drm/i915/gtt: Allow >= 4GB offsets in X86_32 2015-08-14 18:16:30 +02:00
i915_gem_render_state.c drm/i915: Add provision to extend Golden context batch 2015-07-21 09:30:57 +02:00
i915_gem_render_state.h drm/i915: Add provision to extend Golden context batch 2015-07-21 09:30:57 +02:00
i915_gem_shrinker.c drm/i915: Simplify object is-pinned checking for shrinker 2015-04-10 10:58:34 +02:00
i915_gem_stolen.c drm/i915: fix stolen bios_reserved checks 2015-08-14 17:50:38 +02:00
i915_gem_tiling.c Merge tag 'drm-intel-fixes-2015-08-14' into drm-intel-next-fixes 2015-08-14 18:11:30 +02:00
i915_gem_userptr.c drm/i915/userptr: Kill user_size limit check 2015-08-14 18:16:27 +02:00
i915_gem.c drm/i915/bxt: don't allow cached GEM mappings on A stepping 2015-08-26 09:39:14 +02:00
i915_gpu_error.c drm/i915: Integrate GuC-based command submission 2015-08-14 18:16:44 +02:00
i915_guc_reg.h drm/i915: GuC-specific firmware loader 2015-08-14 18:16:39 +02:00
i915_guc_submission.c drm/i915: Integrate GuC-based command submission 2015-08-14 18:16:44 +02:00
i915_ioc32.c Merge tag 'drm-intel-fixes-2015-07-15' into drm-intel-next-queued 2015-07-15 16:36:50 +02:00
i915_irq.c drm/i915/bxt: Add HPD support for DDIA 2015-08-14 18:16:32 +02:00
i915_params.c drm/i915: Add GuC-related module parameters 2015-07-21 08:37:35 +02:00
i915_reg.h drm/i915: Implement PHY lane power gating for CHV 2015-08-26 14:34:41 +02:00
i915_suspend.c drm/i915: use dev_priv for the FBC functions 2015-07-08 11:39:45 +02:00
i915_sysfs.c drm/i915/vlv: fix RC6 residency time calculation 2015-06-15 11:56:37 +02:00
i915_trace_points.c
i915_trace.h drm/i915/gen8: implement alloc/free for 4lvl 2015-08-14 18:16:21 +02:00
i915_vgpu.c
i915_vgpu.h
intel_acpi.c
intel_atomic_plane.c drm/i915: Remove transitional references from intel_plane_atomic_check. 2015-06-22 14:28:29 +02:00
intel_atomic.c drm/i915: remove excessive scaler debugging messages 2015-08-14 18:16:45 +02:00
intel_audio.c Merge tag 'drm-intel-fixes-2015-07-15' into drm-intel-next-queued 2015-07-15 16:36:50 +02:00
intel_bios.c drm/i915: Per-DDI I_boost override 2015-08-14 18:13:09 +02:00
intel_bios.h drm/i915: Per-DDI I_boost override 2015-08-14 18:13:09 +02:00
intel_crt.c drm/i915: Get rid of dpms handling. 2015-08-14 17:50:33 +02:00
intel_csr.c drm/i915/gen9: Removed byte swapping for csr firmware 2015-08-05 11:00:04 +02:00
intel_ddi.c drm/i915: Put back lane_count into intel_dp and add link_rate too 2015-08-26 09:58:19 +02:00
intel_display.c drm/i915: move ibx_digital_port_connected to intel_dp.c 2015-08-26 11:00:16 +02:00
intel_dp_mst.c drm/i915: Put back lane_count into intel_dp and add link_rate too 2015-08-26 09:58:19 +02:00
intel_dp.c drm/i915: Trick CL2 into life on CHV when using pipe B with port B 2015-08-26 14:35:06 +02:00
intel_drv.h drm/i915: Trick CL2 into life on CHV when using pipe B with port B 2015-08-26 14:35:06 +02:00
intel_dsi_panel_vbt.c drm/i915: s/dpio_lock/sb_lock/ 2015-05-28 11:13:51 +02:00
intel_dsi_pll.c drm/i915: Changes required to enable DSI Video Mode on CHT 2015-07-03 07:39:02 +02:00
intel_dsi.c drm/i915: DSI pixel clock check 2015-08-26 10:29:12 +02:00
intel_dsi.h drm/i915: Use the CRC gpio for panel enable/disable 2015-07-21 09:22:43 +02:00
intel_dvo.c drm/i915: DVO pixel clock check 2015-08-26 10:29:20 +02:00
intel_fbc.c drm/i915: fix FBC frontbuffer tracking flushing code 2015-08-05 09:59:44 +02:00
intel_fbdev.c drm/i915/gtt: Allow >= 4GB offsets in X86_32 2015-08-14 18:16:30 +02:00
intel_fifo_underrun.c
intel_frontbuffer.c drm/i915: fix FBC frontbuffer tracking flushing code 2015-08-05 09:59:44 +02:00
intel_guc_fwif.h drm/i915: Implementation of GuC submission client 2015-08-14 18:16:42 +02:00
intel_guc_loader.c drm/i915: Interrupt routing for GuC submission 2015-08-14 18:16:43 +02:00
intel_guc.h drm/i915: Integrate GuC-based command submission 2015-08-14 18:16:44 +02:00
intel_hdmi.c drm/i915: Trick CL2 into life on CHV when using pipe B with port B 2015-08-26 14:35:06 +02:00
intel_hotplug.c drm/i915: don't use HPD_PORT_A as an alias for HPD_NONE 2015-07-22 10:44:51 +02:00
intel_i2c.c Merge branch 'drm-next' of git://people.freedesktop.org/~airlied/linux 2015-06-26 13:18:51 -07:00
intel_lrc.c drm/i915/bxt: work around HW coherency issue when accessing GPU seqno 2015-08-26 09:39:13 +02:00
intel_lrc.h drm/i915: Integrate GuC-based command submission 2015-08-14 18:16:44 +02:00
intel_lvds.c drm/i915: LVDS pixel clock check 2015-08-26 10:29:05 +02:00
intel_mocs.c drm/i915: Added Programming of the MOCS 2015-07-14 17:13:14 +02:00
intel_mocs.h drm/i915: Added Programming of the MOCS 2015-07-14 17:13:14 +02:00
intel_modes.c
intel_opregion.c Merge tag 'drm-intel-fixes-2015-07-15' into drm-intel-next-queued 2015-07-15 16:36:50 +02:00
intel_overlay.c drm/i915: Update intel_ring_begin() to take a request structure 2015-06-23 14:02:29 +02:00
intel_panel.c drm/i915: Backlight control using CRC PMIC based PWM driver 2015-07-21 09:22:48 +02:00
intel_pm.c Merge tag 'topic/drm-misc-2015-07-28' into drm-intel-next-queued 2015-08-06 14:27:09 +02:00
intel_psr.c drm/i915: VLV/CHV PSR: Increase wait delay time before active PSR. 2015-08-05 10:07:44 +02:00
intel_renderstate_gen6.c
intel_renderstate_gen7.c
intel_renderstate_gen8.c
intel_renderstate_gen9.c
intel_renderstate.h
intel_ringbuffer.c drm/i915: Contain the WA_REG macro 2015-08-14 17:50:42 +02:00
intel_ringbuffer.h drm/i915/bxt: work around HW coherency issue when accessing GPU seqno 2015-08-26 09:39:13 +02:00
intel_runtime_pm.c drm/i915: Trick CL2 into life on CHV when using pipe B with port B 2015-08-26 14:35:06 +02:00
intel_sdvo_regs.h
intel_sdvo.c drm/i915: Make some string arrays const 2015-08-26 11:19:36 +02:00
intel_sideband.c drm/i915: s/dpio_lock/sb_lock/ 2015-05-28 11:13:51 +02:00
intel_sprite.c drm/i915: always disable irqs in intel_pipe_update_start 2015-07-15 15:06:02 +02:00
intel_tv.c drm/i915: Use ARRAY_SIZE() instead of hand rolling it 2015-08-26 11:19:30 +02:00
intel_uncore.c drm/i915: Use ARRAY_SIZE() instead of hand rolling it 2015-08-26 11:19:30 +02:00
Kconfig drm/i915: Remove KMS Kconfig option 2015-06-22 16:16:35 +02:00
Makefile drm/i915: Prepare for GuC-based command submission 2015-08-14 18:16:41 +02:00