mirror of
https://github.com/AuxXxilium/linux_dsm_epyc7002.git
synced 2024-12-22 18:32:14 +07:00
143f230533
DTM is the display topology manager. This is needed to communicate with
psp about the display configurations.
This patch adds
-Loading the firmware
-The functions and definitions for communication with the firmware
v2: Fix formatting
Signed-off-by: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com>
Reviewed-by: Harry Wentland <harry.wentland@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
393 lines
12 KiB
C
393 lines
12 KiB
C
/*
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* Copyright 2012 Advanced Micro Devices, Inc.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
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* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
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* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
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* OTHER DEALINGS IN THE SOFTWARE.
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*
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*/
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#ifndef __AMDGPU_UCODE_H__
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#define __AMDGPU_UCODE_H__
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#include "amdgpu_socbb.h"
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struct common_firmware_header {
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uint32_t size_bytes; /* size of the entire header+image(s) in bytes */
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uint32_t header_size_bytes; /* size of just the header in bytes */
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uint16_t header_version_major; /* header version */
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uint16_t header_version_minor; /* header version */
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uint16_t ip_version_major; /* IP version */
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uint16_t ip_version_minor; /* IP version */
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uint32_t ucode_version;
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uint32_t ucode_size_bytes; /* size of ucode in bytes */
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uint32_t ucode_array_offset_bytes; /* payload offset from the start of the header */
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uint32_t crc32; /* crc32 checksum of the payload */
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};
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/* version_major=1, version_minor=0 */
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struct mc_firmware_header_v1_0 {
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struct common_firmware_header header;
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uint32_t io_debug_size_bytes; /* size of debug array in dwords */
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uint32_t io_debug_array_offset_bytes; /* payload offset from the start of the header */
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};
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/* version_major=1, version_minor=0 */
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struct smc_firmware_header_v1_0 {
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struct common_firmware_header header;
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uint32_t ucode_start_addr;
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};
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/* version_major=2, version_minor=0 */
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struct smc_firmware_header_v2_0 {
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struct smc_firmware_header_v1_0 v1_0;
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uint32_t ppt_offset_bytes; /* soft pptable offset */
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uint32_t ppt_size_bytes; /* soft pptable size */
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};
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struct smc_soft_pptable_entry {
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uint32_t id;
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uint32_t ppt_offset_bytes;
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uint32_t ppt_size_bytes;
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};
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/* version_major=2, version_minor=1 */
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struct smc_firmware_header_v2_1 {
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struct smc_firmware_header_v1_0 v1_0;
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uint32_t pptable_count;
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uint32_t pptable_entry_offset;
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};
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/* version_major=1, version_minor=0 */
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struct psp_firmware_header_v1_0 {
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struct common_firmware_header header;
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uint32_t ucode_feature_version;
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uint32_t sos_offset_bytes;
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uint32_t sos_size_bytes;
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};
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/* version_major=1, version_minor=1 */
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struct psp_firmware_header_v1_1 {
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struct psp_firmware_header_v1_0 v1_0;
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uint32_t toc_header_version;
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uint32_t toc_offset_bytes;
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uint32_t toc_size_bytes;
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uint32_t kdb_header_version;
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uint32_t kdb_offset_bytes;
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uint32_t kdb_size_bytes;
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};
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/* version_major=1, version_minor=2 */
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struct psp_firmware_header_v1_2 {
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struct psp_firmware_header_v1_0 v1_0;
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uint32_t reserve[3];
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uint32_t kdb_header_version;
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uint32_t kdb_offset_bytes;
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uint32_t kdb_size_bytes;
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};
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/* version_major=1, version_minor=0 */
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struct ta_firmware_header_v1_0 {
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struct common_firmware_header header;
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uint32_t ta_xgmi_ucode_version;
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uint32_t ta_xgmi_offset_bytes;
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uint32_t ta_xgmi_size_bytes;
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uint32_t ta_ras_ucode_version;
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uint32_t ta_ras_offset_bytes;
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uint32_t ta_ras_size_bytes;
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uint32_t ta_hdcp_ucode_version;
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uint32_t ta_hdcp_offset_bytes;
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uint32_t ta_hdcp_size_bytes;
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uint32_t ta_dtm_ucode_version;
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uint32_t ta_dtm_offset_bytes;
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uint32_t ta_dtm_size_bytes;
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};
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/* version_major=1, version_minor=0 */
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struct gfx_firmware_header_v1_0 {
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struct common_firmware_header header;
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uint32_t ucode_feature_version;
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uint32_t jt_offset; /* jt location */
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uint32_t jt_size; /* size of jt */
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};
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/* version_major=1, version_minor=0 */
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struct mes_firmware_header_v1_0 {
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struct common_firmware_header header;
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uint32_t mes_ucode_version;
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uint32_t mes_ucode_size_bytes;
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uint32_t mes_ucode_offset_bytes;
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uint32_t mes_ucode_data_version;
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uint32_t mes_ucode_data_size_bytes;
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uint32_t mes_ucode_data_offset_bytes;
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uint32_t mes_uc_start_addr_lo;
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uint32_t mes_uc_start_addr_hi;
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uint32_t mes_data_start_addr_lo;
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uint32_t mes_data_start_addr_hi;
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};
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/* version_major=1, version_minor=0 */
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struct rlc_firmware_header_v1_0 {
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struct common_firmware_header header;
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uint32_t ucode_feature_version;
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uint32_t save_and_restore_offset;
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uint32_t clear_state_descriptor_offset;
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uint32_t avail_scratch_ram_locations;
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uint32_t master_pkt_description_offset;
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};
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/* version_major=2, version_minor=0 */
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struct rlc_firmware_header_v2_0 {
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struct common_firmware_header header;
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uint32_t ucode_feature_version;
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uint32_t jt_offset; /* jt location */
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uint32_t jt_size; /* size of jt */
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uint32_t save_and_restore_offset;
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uint32_t clear_state_descriptor_offset;
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uint32_t avail_scratch_ram_locations;
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uint32_t reg_restore_list_size;
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uint32_t reg_list_format_start;
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uint32_t reg_list_format_separate_start;
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uint32_t starting_offsets_start;
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uint32_t reg_list_format_size_bytes; /* size of reg list format array in bytes */
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uint32_t reg_list_format_array_offset_bytes; /* payload offset from the start of the header */
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uint32_t reg_list_size_bytes; /* size of reg list array in bytes */
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uint32_t reg_list_array_offset_bytes; /* payload offset from the start of the header */
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uint32_t reg_list_format_separate_size_bytes; /* size of reg list format array in bytes */
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uint32_t reg_list_format_separate_array_offset_bytes; /* payload offset from the start of the header */
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uint32_t reg_list_separate_size_bytes; /* size of reg list array in bytes */
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uint32_t reg_list_separate_array_offset_bytes; /* payload offset from the start of the header */
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};
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/* version_major=2, version_minor=1 */
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struct rlc_firmware_header_v2_1 {
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struct rlc_firmware_header_v2_0 v2_0;
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uint32_t reg_list_format_direct_reg_list_length; /* length of direct reg list format array */
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uint32_t save_restore_list_cntl_ucode_ver;
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uint32_t save_restore_list_cntl_feature_ver;
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uint32_t save_restore_list_cntl_size_bytes;
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uint32_t save_restore_list_cntl_offset_bytes;
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uint32_t save_restore_list_gpm_ucode_ver;
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uint32_t save_restore_list_gpm_feature_ver;
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uint32_t save_restore_list_gpm_size_bytes;
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uint32_t save_restore_list_gpm_offset_bytes;
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uint32_t save_restore_list_srm_ucode_ver;
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uint32_t save_restore_list_srm_feature_ver;
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uint32_t save_restore_list_srm_size_bytes;
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uint32_t save_restore_list_srm_offset_bytes;
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};
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/* version_major=1, version_minor=0 */
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struct sdma_firmware_header_v1_0 {
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struct common_firmware_header header;
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uint32_t ucode_feature_version;
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uint32_t ucode_change_version;
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uint32_t jt_offset; /* jt location */
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uint32_t jt_size; /* size of jt */
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};
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/* version_major=1, version_minor=1 */
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struct sdma_firmware_header_v1_1 {
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struct sdma_firmware_header_v1_0 v1_0;
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uint32_t digest_size;
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};
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/* gpu info payload */
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struct gpu_info_firmware_v1_0 {
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uint32_t gc_num_se;
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uint32_t gc_num_cu_per_sh;
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uint32_t gc_num_sh_per_se;
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uint32_t gc_num_rb_per_se;
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uint32_t gc_num_tccs;
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uint32_t gc_num_gprs;
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uint32_t gc_num_max_gs_thds;
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uint32_t gc_gs_table_depth;
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uint32_t gc_gsprim_buff_depth;
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uint32_t gc_parameter_cache_depth;
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uint32_t gc_double_offchip_lds_buffer;
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uint32_t gc_wave_size;
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uint32_t gc_max_waves_per_simd;
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uint32_t gc_max_scratch_slots_per_cu;
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uint32_t gc_lds_size;
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};
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struct gpu_info_firmware_v1_1 {
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struct gpu_info_firmware_v1_0 v1_0;
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uint32_t num_sc_per_sh;
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uint32_t num_packer_per_sc;
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};
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/* gpu info payload
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* version_major=1, version_minor=1 */
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struct gpu_info_firmware_v1_2 {
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struct gpu_info_firmware_v1_1 v1_1;
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struct gpu_info_soc_bounding_box_v1_0 soc_bounding_box;
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};
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/* version_major=1, version_minor=0 */
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struct gpu_info_firmware_header_v1_0 {
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struct common_firmware_header header;
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uint16_t version_major; /* version */
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uint16_t version_minor; /* version */
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};
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/* version_major=1, version_minor=0 */
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struct dmcu_firmware_header_v1_0 {
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struct common_firmware_header header;
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uint32_t intv_offset_bytes; /* interrupt vectors offset from end of header, in bytes */
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uint32_t intv_size_bytes; /* size of interrupt vectors, in bytes */
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};
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/* header is fixed size */
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union amdgpu_firmware_header {
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struct common_firmware_header common;
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struct mc_firmware_header_v1_0 mc;
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struct smc_firmware_header_v1_0 smc;
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struct smc_firmware_header_v2_0 smc_v2_0;
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struct psp_firmware_header_v1_0 psp;
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struct psp_firmware_header_v1_1 psp_v1_1;
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struct ta_firmware_header_v1_0 ta;
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struct gfx_firmware_header_v1_0 gfx;
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struct rlc_firmware_header_v1_0 rlc;
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struct rlc_firmware_header_v2_0 rlc_v2_0;
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struct rlc_firmware_header_v2_1 rlc_v2_1;
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struct sdma_firmware_header_v1_0 sdma;
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struct sdma_firmware_header_v1_1 sdma_v1_1;
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struct gpu_info_firmware_header_v1_0 gpu_info;
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struct dmcu_firmware_header_v1_0 dmcu;
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uint8_t raw[0x100];
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};
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/*
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* fw loading support
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*/
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enum AMDGPU_UCODE_ID {
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AMDGPU_UCODE_ID_SDMA0 = 0,
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AMDGPU_UCODE_ID_SDMA1,
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AMDGPU_UCODE_ID_SDMA2,
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AMDGPU_UCODE_ID_SDMA3,
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AMDGPU_UCODE_ID_SDMA4,
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AMDGPU_UCODE_ID_SDMA5,
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AMDGPU_UCODE_ID_SDMA6,
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AMDGPU_UCODE_ID_SDMA7,
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AMDGPU_UCODE_ID_CP_CE,
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AMDGPU_UCODE_ID_CP_PFP,
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AMDGPU_UCODE_ID_CP_ME,
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AMDGPU_UCODE_ID_CP_MEC1,
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AMDGPU_UCODE_ID_CP_MEC1_JT,
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AMDGPU_UCODE_ID_CP_MEC2,
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AMDGPU_UCODE_ID_CP_MEC2_JT,
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AMDGPU_UCODE_ID_CP_MES,
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AMDGPU_UCODE_ID_CP_MES_DATA,
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AMDGPU_UCODE_ID_RLC_G,
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AMDGPU_UCODE_ID_RLC_RESTORE_LIST_CNTL,
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AMDGPU_UCODE_ID_RLC_RESTORE_LIST_GPM_MEM,
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AMDGPU_UCODE_ID_RLC_RESTORE_LIST_SRM_MEM,
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AMDGPU_UCODE_ID_STORAGE,
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AMDGPU_UCODE_ID_SMC,
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AMDGPU_UCODE_ID_UVD,
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AMDGPU_UCODE_ID_UVD1,
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AMDGPU_UCODE_ID_VCE,
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AMDGPU_UCODE_ID_VCN,
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AMDGPU_UCODE_ID_VCN1,
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AMDGPU_UCODE_ID_DMCU_ERAM,
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AMDGPU_UCODE_ID_DMCU_INTV,
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AMDGPU_UCODE_ID_VCN0_RAM,
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AMDGPU_UCODE_ID_VCN1_RAM,
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AMDGPU_UCODE_ID_MAXIMUM,
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};
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/* engine firmware status */
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enum AMDGPU_UCODE_STATUS {
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AMDGPU_UCODE_STATUS_INVALID,
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AMDGPU_UCODE_STATUS_NOT_LOADED,
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AMDGPU_UCODE_STATUS_LOADED,
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};
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enum amdgpu_firmware_load_type {
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AMDGPU_FW_LOAD_DIRECT = 0,
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AMDGPU_FW_LOAD_SMU,
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AMDGPU_FW_LOAD_PSP,
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AMDGPU_FW_LOAD_RLC_BACKDOOR_AUTO,
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};
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/* conform to smu_ucode_xfer_cz.h */
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#define AMDGPU_SDMA0_UCODE_LOADED 0x00000001
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#define AMDGPU_SDMA1_UCODE_LOADED 0x00000002
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#define AMDGPU_CPCE_UCODE_LOADED 0x00000004
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#define AMDGPU_CPPFP_UCODE_LOADED 0x00000008
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#define AMDGPU_CPME_UCODE_LOADED 0x00000010
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#define AMDGPU_CPMEC1_UCODE_LOADED 0x00000020
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#define AMDGPU_CPMEC2_UCODE_LOADED 0x00000040
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#define AMDGPU_CPRLC_UCODE_LOADED 0x00000100
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/* amdgpu firmware info */
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struct amdgpu_firmware_info {
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/* ucode ID */
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enum AMDGPU_UCODE_ID ucode_id;
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/* request_firmware */
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const struct firmware *fw;
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/* starting mc address */
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uint64_t mc_addr;
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/* kernel linear address */
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void *kaddr;
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/* ucode_size_bytes */
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uint32_t ucode_size;
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/* starting tmr mc address */
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uint32_t tmr_mc_addr_lo;
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uint32_t tmr_mc_addr_hi;
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};
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struct amdgpu_firmware {
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struct amdgpu_firmware_info ucode[AMDGPU_UCODE_ID_MAXIMUM];
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enum amdgpu_firmware_load_type load_type;
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struct amdgpu_bo *fw_buf;
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unsigned int fw_size;
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unsigned int max_ucodes;
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/* firmwares are loaded by psp instead of smu from vega10 */
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const struct amdgpu_psp_funcs *funcs;
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struct amdgpu_bo *rbuf;
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struct mutex mutex;
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/* gpu info firmware data pointer */
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const struct firmware *gpu_info_fw;
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void *fw_buf_ptr;
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uint64_t fw_buf_mc;
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};
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void amdgpu_ucode_print_mc_hdr(const struct common_firmware_header *hdr);
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void amdgpu_ucode_print_smc_hdr(const struct common_firmware_header *hdr);
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void amdgpu_ucode_print_gfx_hdr(const struct common_firmware_header *hdr);
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void amdgpu_ucode_print_rlc_hdr(const struct common_firmware_header *hdr);
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void amdgpu_ucode_print_sdma_hdr(const struct common_firmware_header *hdr);
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void amdgpu_ucode_print_psp_hdr(const struct common_firmware_header *hdr);
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void amdgpu_ucode_print_gpu_info_hdr(const struct common_firmware_header *hdr);
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int amdgpu_ucode_validate(const struct firmware *fw);
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bool amdgpu_ucode_hdr_version(union amdgpu_firmware_header *hdr,
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uint16_t hdr_major, uint16_t hdr_minor);
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int amdgpu_ucode_init_bo(struct amdgpu_device *adev);
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int amdgpu_ucode_create_bo(struct amdgpu_device *adev);
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int amdgpu_ucode_sysfs_init(struct amdgpu_device *adev);
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void amdgpu_ucode_free_bo(struct amdgpu_device *adev);
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void amdgpu_ucode_sysfs_fini(struct amdgpu_device *adev);
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enum amdgpu_firmware_load_type
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amdgpu_ucode_get_load_type(struct amdgpu_device *adev, int load_type);
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#endif
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