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b08369a174
It was observed the Host Clock Divider was not written by the driver. It was still set to (default) 0, if not already set by BIOS, which caused garbage on SMBus. This driver adds a parameters which is used to calculate the divider appropriately for a default bitrate of 100 KHz. This new divider is only applied if the clock divider is still default 0. Signed-off-by: Alexander Stein <alexander.stein@systec-electronic.com> Reviewed-by: Jean Delvare <khali@linux-fr.org> Signed-off-by: Wolfram Sang <wolfram@the-dreams.de>
332 lines
9.2 KiB
C
332 lines
9.2 KiB
C
/*
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i2c-isch.c - Linux kernel driver for Intel SCH chipset SMBus
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- Based on i2c-piix4.c
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Copyright (c) 1998 - 2002 Frodo Looijaard <frodol@dds.nl> and
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Philip Edelbrock <phil@netroedge.com>
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- Intel SCH support
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Copyright (c) 2007 - 2008 Jacob Jun Pan <jacob.jun.pan@intel.com>
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This program is free software; you can redistribute it and/or modify
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it under the terms of the GNU General Public License version 2 as
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published by the Free Software Foundation.
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This program is distributed in the hope that it will be useful,
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but WITHOUT ANY WARRANTY; without even the implied warranty of
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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GNU General Public License for more details.
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You should have received a copy of the GNU General Public License
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along with this program; if not, write to the Free Software
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Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
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*/
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/*
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Supports:
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Intel SCH chipsets (AF82US15W, AF82US15L, AF82UL11L)
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Note: we assume there can only be one device, with one SMBus interface.
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*/
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#include <linux/module.h>
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#include <linux/platform_device.h>
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#include <linux/kernel.h>
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#include <linux/delay.h>
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#include <linux/stddef.h>
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#include <linux/ioport.h>
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#include <linux/i2c.h>
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#include <linux/init.h>
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#include <linux/io.h>
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#include <linux/acpi.h>
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/* SCH SMBus address offsets */
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#define SMBHSTCNT (0 + sch_smba)
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#define SMBHSTSTS (1 + sch_smba)
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#define SMBHSTCLK (2 + sch_smba)
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#define SMBHSTADD (4 + sch_smba) /* TSA */
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#define SMBHSTCMD (5 + sch_smba)
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#define SMBHSTDAT0 (6 + sch_smba)
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#define SMBHSTDAT1 (7 + sch_smba)
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#define SMBBLKDAT (0x20 + sch_smba)
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/* Other settings */
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#define MAX_RETRIES 5000
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/* I2C constants */
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#define SCH_QUICK 0x00
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#define SCH_BYTE 0x01
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#define SCH_BYTE_DATA 0x02
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#define SCH_WORD_DATA 0x03
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#define SCH_BLOCK_DATA 0x05
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static unsigned short sch_smba;
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static struct i2c_adapter sch_adapter;
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static int backbone_speed = 33000; /* backbone speed in kHz */
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module_param(backbone_speed, int, S_IRUSR | S_IWUSR);
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MODULE_PARM_DESC(backbone_speed, "Backbone speed in kHz, (default = 33000)");
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/*
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* Start the i2c transaction -- the i2c_access will prepare the transaction
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* and this function will execute it.
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* return 0 for success and others for failure.
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*/
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static int sch_transaction(void)
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{
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int temp;
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int result = 0;
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int retries = 0;
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dev_dbg(&sch_adapter.dev, "Transaction (pre): CNT=%02x, CMD=%02x, "
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"ADD=%02x, DAT0=%02x, DAT1=%02x\n", inb(SMBHSTCNT),
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inb(SMBHSTCMD), inb(SMBHSTADD), inb(SMBHSTDAT0),
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inb(SMBHSTDAT1));
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/* Make sure the SMBus host is ready to start transmitting */
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temp = inb(SMBHSTSTS) & 0x0f;
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if (temp) {
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/* Can not be busy since we checked it in sch_access */
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if (temp & 0x01) {
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dev_dbg(&sch_adapter.dev, "Completion (%02x). "
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"Clear...\n", temp);
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}
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if (temp & 0x06) {
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dev_dbg(&sch_adapter.dev, "SMBus error (%02x). "
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"Resetting...\n", temp);
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}
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outb(temp, SMBHSTSTS);
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temp = inb(SMBHSTSTS) & 0x0f;
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if (temp) {
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dev_err(&sch_adapter.dev,
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"SMBus is not ready: (%02x)\n", temp);
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return -EAGAIN;
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}
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}
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/* start the transaction by setting bit 4 */
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outb(inb(SMBHSTCNT) | 0x10, SMBHSTCNT);
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do {
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usleep_range(100, 200);
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temp = inb(SMBHSTSTS) & 0x0f;
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} while ((temp & 0x08) && (retries++ < MAX_RETRIES));
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/* If the SMBus is still busy, we give up */
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if (retries > MAX_RETRIES) {
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dev_err(&sch_adapter.dev, "SMBus Timeout!\n");
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result = -ETIMEDOUT;
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}
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if (temp & 0x04) {
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result = -EIO;
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dev_dbg(&sch_adapter.dev, "Bus collision! SMBus may be "
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"locked until next hard reset. (sorry!)\n");
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/* Clock stops and slave is stuck in mid-transmission */
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} else if (temp & 0x02) {
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result = -EIO;
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dev_err(&sch_adapter.dev, "Error: no response!\n");
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} else if (temp & 0x01) {
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dev_dbg(&sch_adapter.dev, "Post complete!\n");
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outb(temp, SMBHSTSTS);
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temp = inb(SMBHSTSTS) & 0x07;
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if (temp & 0x06) {
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/* Completion clear failed */
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dev_dbg(&sch_adapter.dev, "Failed reset at end of "
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"transaction (%02x), Bus error!\n", temp);
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}
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} else {
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result = -ENXIO;
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dev_dbg(&sch_adapter.dev, "No such address.\n");
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}
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dev_dbg(&sch_adapter.dev, "Transaction (post): CNT=%02x, CMD=%02x, "
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"ADD=%02x, DAT0=%02x, DAT1=%02x\n", inb(SMBHSTCNT),
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inb(SMBHSTCMD), inb(SMBHSTADD), inb(SMBHSTDAT0),
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inb(SMBHSTDAT1));
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return result;
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}
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/*
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* This is the main access entry for i2c-sch access
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* adap is i2c_adapter pointer, addr is the i2c device bus address, read_write
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* (0 for read and 1 for write), size is i2c transaction type and data is the
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* union of transaction for data to be transferred or data read from bus.
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* return 0 for success and others for failure.
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*/
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static s32 sch_access(struct i2c_adapter *adap, u16 addr,
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unsigned short flags, char read_write,
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u8 command, int size, union i2c_smbus_data *data)
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{
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int i, len, temp, rc;
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/* Make sure the SMBus host is not busy */
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temp = inb(SMBHSTSTS) & 0x0f;
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if (temp & 0x08) {
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dev_dbg(&sch_adapter.dev, "SMBus busy (%02x)\n", temp);
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return -EAGAIN;
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}
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temp = inw(SMBHSTCLK);
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if (!temp) {
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/*
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* We can't determine if we have 33 or 25 MHz clock for
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* SMBus, so expect 33 MHz and calculate a bus clock of
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* 100 kHz. If we actually run at 25 MHz the bus will be
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* run ~75 kHz instead which should do no harm.
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*/
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dev_notice(&sch_adapter.dev,
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"Clock divider unitialized. Setting defaults\n");
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outw(backbone_speed / (4 * 100), SMBHSTCLK);
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}
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dev_dbg(&sch_adapter.dev, "access size: %d %s\n", size,
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(read_write)?"READ":"WRITE");
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switch (size) {
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case I2C_SMBUS_QUICK:
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outb((addr << 1) | read_write, SMBHSTADD);
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size = SCH_QUICK;
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break;
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case I2C_SMBUS_BYTE:
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outb((addr << 1) | read_write, SMBHSTADD);
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if (read_write == I2C_SMBUS_WRITE)
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outb(command, SMBHSTCMD);
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size = SCH_BYTE;
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break;
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case I2C_SMBUS_BYTE_DATA:
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outb((addr << 1) | read_write, SMBHSTADD);
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outb(command, SMBHSTCMD);
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if (read_write == I2C_SMBUS_WRITE)
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outb(data->byte, SMBHSTDAT0);
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size = SCH_BYTE_DATA;
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break;
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case I2C_SMBUS_WORD_DATA:
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outb((addr << 1) | read_write, SMBHSTADD);
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outb(command, SMBHSTCMD);
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if (read_write == I2C_SMBUS_WRITE) {
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outb(data->word & 0xff, SMBHSTDAT0);
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outb((data->word & 0xff00) >> 8, SMBHSTDAT1);
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}
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size = SCH_WORD_DATA;
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break;
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case I2C_SMBUS_BLOCK_DATA:
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outb((addr << 1) | read_write, SMBHSTADD);
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outb(command, SMBHSTCMD);
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if (read_write == I2C_SMBUS_WRITE) {
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len = data->block[0];
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if (len == 0 || len > I2C_SMBUS_BLOCK_MAX)
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return -EINVAL;
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outb(len, SMBHSTDAT0);
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for (i = 1; i <= len; i++)
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outb(data->block[i], SMBBLKDAT+i-1);
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}
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size = SCH_BLOCK_DATA;
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break;
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default:
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dev_warn(&adap->dev, "Unsupported transaction %d\n", size);
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return -EOPNOTSUPP;
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}
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dev_dbg(&sch_adapter.dev, "write size %d to 0x%04x\n", size, SMBHSTCNT);
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outb((inb(SMBHSTCNT) & 0xb0) | (size & 0x7), SMBHSTCNT);
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rc = sch_transaction();
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if (rc) /* Error in transaction */
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return rc;
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if ((read_write == I2C_SMBUS_WRITE) || (size == SCH_QUICK))
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return 0;
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switch (size) {
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case SCH_BYTE:
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case SCH_BYTE_DATA:
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data->byte = inb(SMBHSTDAT0);
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break;
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case SCH_WORD_DATA:
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data->word = inb(SMBHSTDAT0) + (inb(SMBHSTDAT1) << 8);
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break;
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case SCH_BLOCK_DATA:
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data->block[0] = inb(SMBHSTDAT0);
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if (data->block[0] == 0 || data->block[0] > I2C_SMBUS_BLOCK_MAX)
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return -EPROTO;
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for (i = 1; i <= data->block[0]; i++)
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data->block[i] = inb(SMBBLKDAT+i-1);
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break;
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}
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return 0;
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}
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static u32 sch_func(struct i2c_adapter *adapter)
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{
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return I2C_FUNC_SMBUS_QUICK | I2C_FUNC_SMBUS_BYTE |
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I2C_FUNC_SMBUS_BYTE_DATA | I2C_FUNC_SMBUS_WORD_DATA |
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I2C_FUNC_SMBUS_BLOCK_DATA;
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}
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static const struct i2c_algorithm smbus_algorithm = {
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.smbus_xfer = sch_access,
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.functionality = sch_func,
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};
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static struct i2c_adapter sch_adapter = {
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.owner = THIS_MODULE,
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.class = I2C_CLASS_HWMON | I2C_CLASS_SPD,
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.algo = &smbus_algorithm,
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};
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static int smbus_sch_probe(struct platform_device *dev)
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{
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struct resource *res;
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int retval;
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res = platform_get_resource(dev, IORESOURCE_IO, 0);
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if (!res)
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return -EBUSY;
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if (!request_region(res->start, resource_size(res), dev->name)) {
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dev_err(&dev->dev, "SMBus region 0x%x already in use!\n",
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sch_smba);
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return -EBUSY;
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}
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sch_smba = res->start;
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dev_dbg(&dev->dev, "SMBA = 0x%X\n", sch_smba);
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/* set up the sysfs linkage to our parent device */
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sch_adapter.dev.parent = &dev->dev;
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snprintf(sch_adapter.name, sizeof(sch_adapter.name),
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"SMBus SCH adapter at %04x", sch_smba);
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retval = i2c_add_adapter(&sch_adapter);
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if (retval) {
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dev_err(&dev->dev, "Couldn't register adapter!\n");
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release_region(res->start, resource_size(res));
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sch_smba = 0;
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}
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return retval;
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}
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static int smbus_sch_remove(struct platform_device *pdev)
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{
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struct resource *res;
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if (sch_smba) {
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i2c_del_adapter(&sch_adapter);
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res = platform_get_resource(pdev, IORESOURCE_IO, 0);
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release_region(res->start, resource_size(res));
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sch_smba = 0;
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}
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return 0;
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}
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static struct platform_driver smbus_sch_driver = {
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.driver = {
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.name = "isch_smbus",
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.owner = THIS_MODULE,
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},
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.probe = smbus_sch_probe,
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.remove = smbus_sch_remove,
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};
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module_platform_driver(smbus_sch_driver);
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MODULE_AUTHOR("Jacob Pan <jacob.jun.pan@intel.com>");
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MODULE_DESCRIPTION("Intel SCH SMBus driver");
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MODULE_LICENSE("GPL");
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MODULE_ALIAS("platform:isch_smbus");
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