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https://github.com/AuxXxilium/linux_dsm_epyc7002.git
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b1f378ab53
In tuning mode of operation, when TBCTL[TB_EN] is set, eSDHC may report one of the following errors : 1)Tuning error while running tuning operation where SYSCTL2[SAMPCLKSEL] will not get set even when SYSCTL2[EXTN] is reset. OR 2)Data transaction error (e.g. IRQSTAT[DCE], IRQSTAT[DEBE]) during data transaction errors. This issue occurs when the data window sampled within eSDHC is in full cycle. So, in that case, eSDHC is not able to find out the start and end points of the data window and sets the sampling pointer at default location (which is middle of the internal SD clock). If this sampling point coincides with the data eye boundary, then it can result in the above mentioned errors. Impact: Tuning mode of operation for SDR50, SDR104 or HS200 speed modes may not work properly Workaround: In case eSDHC reports tuning error or data errors in tuning mode of operation, by add the erratum A008171 support to fix the issue. Signed-off-by: Yinbo Zhu <yinbo.zhu@nxp.com> Acked-by: Adrian Hunter <adrian.hunter@intel.com> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
72 lines
2.0 KiB
C
72 lines
2.0 KiB
C
/*
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* Freescale eSDHC controller driver generics for OF and pltfm.
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*
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* Copyright (c) 2007 Freescale Semiconductor, Inc.
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* Copyright (c) 2009 MontaVista Software, Inc.
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* Copyright (c) 2010 Pengutronix e.K.
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* Author: Wolfram Sang <w.sang@pengutronix.de>
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License.
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*/
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#ifndef _DRIVERS_MMC_SDHCI_ESDHC_H
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#define _DRIVERS_MMC_SDHCI_ESDHC_H
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/*
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* Ops and quirks for the Freescale eSDHC controller.
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*/
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#define ESDHC_DEFAULT_QUIRKS (SDHCI_QUIRK_FORCE_BLK_SZ_2048 | \
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SDHCI_QUIRK_32BIT_DMA_ADDR | \
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SDHCI_QUIRK_NO_BUSY_IRQ | \
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SDHCI_QUIRK_DATA_TIMEOUT_USES_SDCLK | \
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SDHCI_QUIRK_PIO_NEEDS_DELAY | \
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SDHCI_QUIRK_NO_HISPD_BIT)
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/* pltfm-specific */
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#define ESDHC_HOST_CONTROL_LE 0x20
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/*
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* eSDHC register definition
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*/
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/* Present State Register */
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#define ESDHC_PRSSTAT 0x24
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#define ESDHC_CLOCK_STABLE 0x00000008
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/* Protocol Control Register */
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#define ESDHC_PROCTL 0x28
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#define ESDHC_VOLT_SEL 0x00000400
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#define ESDHC_CTRL_4BITBUS (0x1 << 1)
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#define ESDHC_CTRL_8BITBUS (0x2 << 1)
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#define ESDHC_CTRL_BUSWIDTH_MASK (0x3 << 1)
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#define ESDHC_HOST_CONTROL_RES 0x01
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/* System Control Register */
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#define ESDHC_SYSTEM_CONTROL 0x2c
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#define ESDHC_CLOCK_MASK 0x0000fff0
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#define ESDHC_PREDIV_SHIFT 8
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#define ESDHC_DIVIDER_SHIFT 4
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#define ESDHC_CLOCK_SDCLKEN 0x00000008
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#define ESDHC_CLOCK_PEREN 0x00000004
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#define ESDHC_CLOCK_HCKEN 0x00000002
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#define ESDHC_CLOCK_IPGEN 0x00000001
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/* Host Controller Capabilities Register 2 */
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#define ESDHC_CAPABILITIES_1 0x114
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/* Tuning Block Control Register */
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#define ESDHC_TBCTL 0x120
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#define ESDHC_TB_EN 0x00000004
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#define ESDHC_TBPTR 0x128
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/* Control Register for DMA transfer */
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#define ESDHC_DMA_SYSCTL 0x40c
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#define ESDHC_PERIPHERAL_CLK_SEL 0x00080000
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#define ESDHC_FLUSH_ASYNC_FIFO 0x00040000
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#define ESDHC_DMA_SNOOP 0x00000040
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#endif /* _DRIVERS_MMC_SDHCI_ESDHC_H */
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