Andy Lutomirski 1e02ce4ccc x86: Store a per-cpu shadow copy of CR4 ... Context switches and TLB flushes can change individual bits of CR4. CR4 reads take several cycles, so store a shadow copy of CR4 in a per-cpu variable. To avoid wasting a cache line, I added the CR4 shadow to cpu_tlbstate, which is already touched in switch_mm. The heaviest users of the cr4 shadow will be switch_mm and __switch_to_xtra, and __switch_to_xtra is called shortly after switch_mm during context switch, so the cacheline is likely to be hot. Signed-off-by: Andy Lutomirski <luto@amacapital.net> Reviewed-by: Thomas Gleixner <tglx@linutronix.de> Signed-off-by: Peter Zijlstra (Intel) <peterz@infradead.org> Cc: Kees Cook <keescook@chromium.org> Cc: Andrea Arcangeli <aarcange@redhat.com> Cc: Vince Weaver <vince@deater.net> Cc: "hillf.zj" <hillf.zj@alibaba-inc.com> Cc: Valdis Kletnieks <Valdis.Kletnieks@vt.edu> Cc: Paul Mackerras <paulus@samba.org> Cc: Arnaldo Carvalho de Melo <acme@kernel.org> Cc: Linus Torvalds <torvalds@linux-foundation.org> Link: http://lkml.kernel.org/r/3a54dd3353fffbf84804398e00dfdc5b7c1afd7d.1414190806.git.luto@amacapital.net Signed-off-by: Ingo Molnar <mingo@kernel.org>		2015-02-04 12:10:42 +01:00
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cpu.c	x86: Store a per-cpu shadow copy of CR4	2015-02-04 12:10:42 +01:00
hibernate_32.c	nosave: consolidate __nosave_{begin,end} in <asm/sections.h>	2014-10-09 22:26:04 -04:00
hibernate_64.c	nosave: consolidate __nosave_{begin,end} in <asm/sections.h>	2014-10-09 22:26:04 -04:00
hibernate_asm_32.S	x86, gdt, hibernate: Store/load GDT for hibernate path.	2013-05-02 11:27:35 -07:00
hibernate_asm_64.S	x86, gdt, hibernate: Store/load GDT for hibernate path.	2013-05-02 11:27:35 -07:00
Makefile	x86: Fix resume from suspend when CONFIG_CC_STACKPROTECTOR	2009-07-08 13:20:13 +02:00