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https://github.com/AuxXxilium/linux_dsm_epyc7002.git
synced 2025-01-14 13:46:11 +07:00
05e6a5a635
It's easier to understand and maintain enable flags of cq using a single field in type of u32 than defining a field for every flags in the structure hns_roce_cq, and we can add new flags for features more conveniently in the future. Link: https://lore.kernel.org/r/1589982799-28728-3-git-send-email-liweihang@huawei.com Signed-off-by: Lang Cheng <chenglang@huawei.com> Signed-off-by: Weihang Li <liweihang@huawei.com> Signed-off-by: Jason Gunthorpe <jgg@mellanox.com>
397 lines
11 KiB
C
397 lines
11 KiB
C
/*
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* Copyright (c) 2016 Hisilicon Limited.
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*
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* This software is available to you under a choice of one of two
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* licenses. You may choose to be licensed under the terms of the GNU
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* General Public License (GPL) Version 2, available from the file
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* COPYING in the main directory of this source tree, or the
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* OpenIB.org BSD license below:
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*
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* Redistribution and use in source and binary forms, with or
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* without modification, are permitted provided that the following
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* conditions are met:
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*
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* - Redistributions of source code must retain the above
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* copyright notice, this list of conditions and the following
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* disclaimer.
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*
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* - Redistributions in binary form must reproduce the above
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* copyright notice, this list of conditions and the following
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* disclaimer in the documentation and/or other materials
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* provided with the distribution.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
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* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
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* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
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* NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
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* BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
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* ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
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* CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
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* SOFTWARE.
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*/
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#include <linux/platform_device.h>
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#include <rdma/ib_umem.h>
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#include <rdma/uverbs_ioctl.h>
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#include "hns_roce_device.h"
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#include "hns_roce_cmd.h"
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#include "hns_roce_hem.h"
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#include <rdma/hns-abi.h>
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#include "hns_roce_common.h"
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static int alloc_cqc(struct hns_roce_dev *hr_dev, struct hns_roce_cq *hr_cq)
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{
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struct hns_roce_cmd_mailbox *mailbox;
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struct hns_roce_cq_table *cq_table;
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struct ib_device *ibdev = &hr_dev->ib_dev;
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u64 mtts[MTT_MIN_COUNT] = { 0 };
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dma_addr_t dma_handle;
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int ret;
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ret = hns_roce_mtr_find(hr_dev, &hr_cq->mtr, 0, mtts, ARRAY_SIZE(mtts),
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&dma_handle);
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if (ret < 1) {
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ibdev_err(ibdev, "Failed to find CQ mtr\n");
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return -EINVAL;
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}
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cq_table = &hr_dev->cq_table;
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ret = hns_roce_bitmap_alloc(&cq_table->bitmap, &hr_cq->cqn);
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if (ret) {
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ibdev_err(ibdev, "Failed to alloc CQ bitmap, err %d\n", ret);
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return ret;
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}
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/* Get CQC memory HEM(Hardware Entry Memory) table */
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ret = hns_roce_table_get(hr_dev, &cq_table->table, hr_cq->cqn);
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if (ret) {
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ibdev_err(ibdev, "Failed to get CQ(0x%lx) context, err %d\n",
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hr_cq->cqn, ret);
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goto err_out;
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}
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ret = xa_err(xa_store(&cq_table->array, hr_cq->cqn, hr_cq, GFP_KERNEL));
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if (ret) {
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ibdev_err(ibdev, "Failed to xa_store CQ\n");
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goto err_put;
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}
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/* Allocate mailbox memory */
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mailbox = hns_roce_alloc_cmd_mailbox(hr_dev);
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if (IS_ERR(mailbox)) {
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ret = PTR_ERR(mailbox);
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goto err_xa;
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}
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hr_dev->hw->write_cqc(hr_dev, hr_cq, mailbox->buf, mtts, dma_handle);
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/* Send mailbox to hw */
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ret = hns_roce_cmd_mbox(hr_dev, mailbox->dma, 0, hr_cq->cqn, 0,
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HNS_ROCE_CMD_CREATE_CQC, HNS_ROCE_CMD_TIMEOUT_MSECS);
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hns_roce_free_cmd_mailbox(hr_dev, mailbox);
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if (ret) {
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ibdev_err(ibdev,
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"Failed to send create cmd for CQ(0x%lx), err %d\n",
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hr_cq->cqn, ret);
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goto err_xa;
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}
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hr_cq->cons_index = 0;
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hr_cq->arm_sn = 1;
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atomic_set(&hr_cq->refcount, 1);
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init_completion(&hr_cq->free);
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return 0;
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err_xa:
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xa_erase(&cq_table->array, hr_cq->cqn);
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err_put:
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hns_roce_table_put(hr_dev, &cq_table->table, hr_cq->cqn);
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err_out:
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hns_roce_bitmap_free(&cq_table->bitmap, hr_cq->cqn, BITMAP_NO_RR);
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return ret;
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}
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static void free_cqc(struct hns_roce_dev *hr_dev, struct hns_roce_cq *hr_cq)
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{
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struct hns_roce_cq_table *cq_table = &hr_dev->cq_table;
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struct device *dev = hr_dev->dev;
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int ret;
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ret = hns_roce_cmd_mbox(hr_dev, 0, 0, hr_cq->cqn, 1,
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HNS_ROCE_CMD_DESTROY_CQC,
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HNS_ROCE_CMD_TIMEOUT_MSECS);
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if (ret)
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dev_err(dev, "DESTROY_CQ failed (%d) for CQN %06lx\n", ret,
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hr_cq->cqn);
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xa_erase(&cq_table->array, hr_cq->cqn);
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/* Waiting interrupt process procedure carried out */
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synchronize_irq(hr_dev->eq_table.eq[hr_cq->vector].irq);
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/* wait for all interrupt processed */
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if (atomic_dec_and_test(&hr_cq->refcount))
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complete(&hr_cq->free);
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wait_for_completion(&hr_cq->free);
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hns_roce_table_put(hr_dev, &cq_table->table, hr_cq->cqn);
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hns_roce_bitmap_free(&cq_table->bitmap, hr_cq->cqn, BITMAP_NO_RR);
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}
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static int alloc_cq_buf(struct hns_roce_dev *hr_dev, struct hns_roce_cq *hr_cq,
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struct ib_udata *udata, unsigned long addr)
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{
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struct ib_device *ibdev = &hr_dev->ib_dev;
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struct hns_roce_buf_attr buf_attr = {};
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int err;
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buf_attr.page_shift = hr_dev->caps.cqe_buf_pg_sz + HNS_HW_PAGE_SHIFT;
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buf_attr.region[0].size = hr_cq->cq_depth * hr_dev->caps.cq_entry_sz;
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buf_attr.region[0].hopnum = hr_dev->caps.cqe_hop_num;
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buf_attr.region_count = 1;
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buf_attr.fixed_page = true;
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err = hns_roce_mtr_create(hr_dev, &hr_cq->mtr, &buf_attr,
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hr_dev->caps.cqe_ba_pg_sz + HNS_HW_PAGE_SHIFT,
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udata, addr);
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if (err)
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ibdev_err(ibdev, "Failed to alloc CQ mtr, err %d\n", err);
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return err;
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}
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static void free_cq_buf(struct hns_roce_dev *hr_dev, struct hns_roce_cq *hr_cq)
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{
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hns_roce_mtr_destroy(hr_dev, &hr_cq->mtr);
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}
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static int alloc_cq_db(struct hns_roce_dev *hr_dev, struct hns_roce_cq *hr_cq,
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struct ib_udata *udata, unsigned long addr,
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struct hns_roce_ib_create_cq_resp *resp)
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{
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bool has_db = hr_dev->caps.flags & HNS_ROCE_CAP_FLAG_RECORD_DB;
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struct hns_roce_ucontext *uctx;
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int err;
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if (udata) {
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if (has_db &&
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udata->outlen >= offsetofend(typeof(*resp), cap_flags)) {
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uctx = rdma_udata_to_drv_context(udata,
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struct hns_roce_ucontext, ibucontext);
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err = hns_roce_db_map_user(uctx, udata, addr,
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&hr_cq->db);
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if (err)
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return err;
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hr_cq->flags |= HNS_ROCE_CQ_FLAG_RECORD_DB;
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resp->cap_flags |= HNS_ROCE_CQ_FLAG_RECORD_DB;
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}
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} else {
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if (has_db) {
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err = hns_roce_alloc_db(hr_dev, &hr_cq->db, 1);
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if (err)
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return err;
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hr_cq->set_ci_db = hr_cq->db.db_record;
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*hr_cq->set_ci_db = 0;
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hr_cq->flags |= HNS_ROCE_CQ_FLAG_RECORD_DB;
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}
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hr_cq->cq_db_l = hr_dev->reg_base + hr_dev->odb_offset +
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DB_REG_OFFSET * hr_dev->priv_uar.index;
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}
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return 0;
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}
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static void free_cq_db(struct hns_roce_dev *hr_dev, struct hns_roce_cq *hr_cq,
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struct ib_udata *udata)
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{
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struct hns_roce_ucontext *uctx;
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if (!(hr_cq->flags & HNS_ROCE_CQ_FLAG_RECORD_DB))
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return;
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hr_cq->flags &= ~HNS_ROCE_CQ_FLAG_RECORD_DB;
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if (udata) {
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uctx = rdma_udata_to_drv_context(udata,
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struct hns_roce_ucontext,
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ibucontext);
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hns_roce_db_unmap_user(uctx, &hr_cq->db);
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} else {
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hns_roce_free_db(hr_dev, &hr_cq->db);
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}
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}
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int hns_roce_create_cq(struct ib_cq *ib_cq, const struct ib_cq_init_attr *attr,
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struct ib_udata *udata)
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{
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struct hns_roce_dev *hr_dev = to_hr_dev(ib_cq->device);
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struct hns_roce_ib_create_cq_resp resp = {};
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struct hns_roce_cq *hr_cq = to_hr_cq(ib_cq);
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struct ib_device *ibdev = &hr_dev->ib_dev;
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struct hns_roce_ib_create_cq ucmd = {};
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int vector = attr->comp_vector;
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u32 cq_entries = attr->cqe;
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int ret;
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if (cq_entries < 1 || cq_entries > hr_dev->caps.max_cqes) {
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ibdev_err(ibdev, "Failed to check CQ count %d max=%d\n",
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cq_entries, hr_dev->caps.max_cqes);
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return -EINVAL;
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}
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if (vector >= hr_dev->caps.num_comp_vectors) {
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ibdev_err(ibdev, "Failed to check CQ vector=%d max=%d\n",
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vector, hr_dev->caps.num_comp_vectors);
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return -EINVAL;
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}
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cq_entries = max(cq_entries, hr_dev->caps.min_cqes);
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cq_entries = roundup_pow_of_two(cq_entries);
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hr_cq->ib_cq.cqe = cq_entries - 1; /* used as cqe index */
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hr_cq->cq_depth = cq_entries;
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hr_cq->vector = vector;
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spin_lock_init(&hr_cq->lock);
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INIT_LIST_HEAD(&hr_cq->sq_list);
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INIT_LIST_HEAD(&hr_cq->rq_list);
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if (udata) {
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ret = ib_copy_from_udata(&ucmd, udata, sizeof(ucmd));
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if (ret) {
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ibdev_err(ibdev, "Failed to copy CQ udata, err %d\n",
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ret);
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return ret;
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}
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}
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ret = alloc_cq_buf(hr_dev, hr_cq, udata, ucmd.buf_addr);
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if (ret) {
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ibdev_err(ibdev, "Failed to alloc CQ buf, err %d\n", ret);
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return ret;
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}
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ret = alloc_cq_db(hr_dev, hr_cq, udata, ucmd.db_addr, &resp);
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if (ret) {
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ibdev_err(ibdev, "Failed to alloc CQ db, err %d\n", ret);
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goto err_cq_buf;
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}
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ret = alloc_cqc(hr_dev, hr_cq);
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if (ret) {
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ibdev_err(ibdev, "Failed to alloc CQ context, err %d\n", ret);
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goto err_cq_db;
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}
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/*
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* For the QP created by kernel space, tptr value should be initialized
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* to zero; For the QP created by user space, it will cause synchronous
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* problems if tptr is set to zero here, so we initialze it in user
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* space.
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*/
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if (!udata && hr_cq->tptr_addr)
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*hr_cq->tptr_addr = 0;
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if (udata) {
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resp.cqn = hr_cq->cqn;
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ret = ib_copy_to_udata(udata, &resp, sizeof(resp));
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if (ret)
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goto err_cqc;
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}
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return 0;
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err_cqc:
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free_cqc(hr_dev, hr_cq);
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err_cq_db:
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free_cq_db(hr_dev, hr_cq, udata);
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err_cq_buf:
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free_cq_buf(hr_dev, hr_cq);
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return ret;
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}
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void hns_roce_destroy_cq(struct ib_cq *ib_cq, struct ib_udata *udata)
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{
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struct hns_roce_dev *hr_dev = to_hr_dev(ib_cq->device);
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struct hns_roce_cq *hr_cq = to_hr_cq(ib_cq);
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if (hr_dev->hw->destroy_cq)
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hr_dev->hw->destroy_cq(ib_cq, udata);
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free_cq_buf(hr_dev, hr_cq);
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free_cq_db(hr_dev, hr_cq, udata);
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free_cqc(hr_dev, hr_cq);
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}
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void hns_roce_cq_completion(struct hns_roce_dev *hr_dev, u32 cqn)
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{
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struct hns_roce_cq *hr_cq;
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struct ib_cq *ibcq;
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hr_cq = xa_load(&hr_dev->cq_table.array,
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cqn & (hr_dev->caps.num_cqs - 1));
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if (!hr_cq) {
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dev_warn(hr_dev->dev, "Completion event for bogus CQ 0x%06x\n",
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cqn);
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return;
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}
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++hr_cq->arm_sn;
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ibcq = &hr_cq->ib_cq;
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if (ibcq->comp_handler)
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ibcq->comp_handler(ibcq, ibcq->cq_context);
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}
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void hns_roce_cq_event(struct hns_roce_dev *hr_dev, u32 cqn, int event_type)
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{
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struct device *dev = hr_dev->dev;
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struct hns_roce_cq *hr_cq;
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struct ib_event event;
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struct ib_cq *ibcq;
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hr_cq = xa_load(&hr_dev->cq_table.array,
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cqn & (hr_dev->caps.num_cqs - 1));
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if (!hr_cq) {
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dev_warn(dev, "Async event for bogus CQ 0x%06x\n", cqn);
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return;
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}
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if (event_type != HNS_ROCE_EVENT_TYPE_CQ_ID_INVALID &&
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event_type != HNS_ROCE_EVENT_TYPE_CQ_ACCESS_ERROR &&
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event_type != HNS_ROCE_EVENT_TYPE_CQ_OVERFLOW) {
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dev_err(dev, "Unexpected event type 0x%x on CQ 0x%06x\n",
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event_type, cqn);
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return;
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}
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atomic_inc(&hr_cq->refcount);
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ibcq = &hr_cq->ib_cq;
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if (ibcq->event_handler) {
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event.device = ibcq->device;
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event.element.cq = ibcq;
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event.event = IB_EVENT_CQ_ERR;
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ibcq->event_handler(&event, ibcq->cq_context);
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}
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if (atomic_dec_and_test(&hr_cq->refcount))
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complete(&hr_cq->free);
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}
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int hns_roce_init_cq_table(struct hns_roce_dev *hr_dev)
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{
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struct hns_roce_cq_table *cq_table = &hr_dev->cq_table;
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xa_init(&cq_table->array);
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return hns_roce_bitmap_init(&cq_table->bitmap, hr_dev->caps.num_cqs,
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hr_dev->caps.num_cqs - 1,
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hr_dev->caps.reserved_cqs, 0);
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}
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void hns_roce_cleanup_cq_table(struct hns_roce_dev *hr_dev)
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{
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hns_roce_bitmap_cleanup(&hr_dev->cq_table.bitmap);
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}
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