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74a0496748
ADI is a new feature supported on SPARC M7 and newer processors to allow hardware to catch rogue accesses to memory. ADI is supported for data fetches only and not instruction fetches. An app can enable ADI on its data pages, set version tags on them and use versioned addresses to access the data pages. Upper bits of the address contain the version tag. On M7 processors, upper four bits (bits 63-60) contain the version tag. If a rogue app attempts to access ADI enabled data pages, its access is blocked and processor generates an exception. Please see Documentation/sparc/adi.txt for further details. This patch extends mprotect to enable ADI (TSTATE.mcde), enable/disable MCD (Memory Corruption Detection) on selected memory ranges, enable TTE.mcd in PTEs, return ADI parameters to userspace and save/restore ADI version tags on page swap out/in or migration. ADI is not enabled by default for any task. A task must explicitly enable ADI on a memory range and set version tag for ADI to be effective for the task. Signed-off-by: Khalid Aziz <khalid.aziz@oracle.com> Cc: Khalid Aziz <khalid@gonehiking.org> Reviewed-by: Anthony Yznaga <anthony.yznaga@oracle.com> Signed-off-by: David S. Miller <davem@davemloft.net>
130 lines
3.9 KiB
C
130 lines
3.9 KiB
C
/* SPDX-License-Identifier: GPL-2.0 */
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#ifndef __MMU_H
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#define __MMU_H
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#include <linux/const.h>
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#include <asm/page.h>
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#include <asm/hypervisor.h>
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#define CTX_NR_BITS 13
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#define TAG_CONTEXT_BITS ((_AC(1,UL) << CTX_NR_BITS) - _AC(1,UL))
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/* UltraSPARC-III+ and later have a feature whereby you can
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* select what page size the various Data-TLB instances in the
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* chip. In order to gracefully support this, we put the version
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* field in a spot outside of the areas of the context register
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* where this parameter is specified.
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*/
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#define CTX_VERSION_SHIFT 22
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#define CTX_VERSION_MASK ((~0UL) << CTX_VERSION_SHIFT)
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#define CTX_PGSZ_8KB _AC(0x0,UL)
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#define CTX_PGSZ_64KB _AC(0x1,UL)
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#define CTX_PGSZ_512KB _AC(0x2,UL)
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#define CTX_PGSZ_4MB _AC(0x3,UL)
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#define CTX_PGSZ_BITS _AC(0x7,UL)
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#define CTX_PGSZ0_NUC_SHIFT 61
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#define CTX_PGSZ1_NUC_SHIFT 58
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#define CTX_PGSZ0_SHIFT 16
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#define CTX_PGSZ1_SHIFT 19
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#define CTX_PGSZ_MASK ((CTX_PGSZ_BITS << CTX_PGSZ0_SHIFT) | \
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(CTX_PGSZ_BITS << CTX_PGSZ1_SHIFT))
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#define CTX_PGSZ_BASE CTX_PGSZ_8KB
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#define CTX_PGSZ_HUGE CTX_PGSZ_4MB
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#define CTX_PGSZ_KERN CTX_PGSZ_4MB
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/* Thus, when running on UltraSPARC-III+ and later, we use the following
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* PRIMARY_CONTEXT register values for the kernel context.
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*/
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#define CTX_CHEETAH_PLUS_NUC \
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((CTX_PGSZ_KERN << CTX_PGSZ0_NUC_SHIFT) | \
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(CTX_PGSZ_BASE << CTX_PGSZ1_NUC_SHIFT))
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#define CTX_CHEETAH_PLUS_CTX0 \
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((CTX_PGSZ_KERN << CTX_PGSZ0_SHIFT) | \
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(CTX_PGSZ_BASE << CTX_PGSZ1_SHIFT))
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/* If you want "the TLB context number" use CTX_NR_MASK. If you
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* want "the bits I program into the context registers" use
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* CTX_HW_MASK.
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*/
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#define CTX_NR_MASK TAG_CONTEXT_BITS
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#define CTX_HW_MASK (CTX_NR_MASK | CTX_PGSZ_MASK)
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#define CTX_FIRST_VERSION BIT(CTX_VERSION_SHIFT)
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#define CTX_VALID(__ctx) \
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(!(((__ctx.sparc64_ctx_val) ^ tlb_context_cache) & CTX_VERSION_MASK))
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#define CTX_HWBITS(__ctx) ((__ctx.sparc64_ctx_val) & CTX_HW_MASK)
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#define CTX_NRBITS(__ctx) ((__ctx.sparc64_ctx_val) & CTX_NR_MASK)
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#ifndef __ASSEMBLY__
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#define TSB_ENTRY_ALIGNMENT 16
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struct tsb {
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unsigned long tag;
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unsigned long pte;
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} __attribute__((aligned(TSB_ENTRY_ALIGNMENT)));
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void __tsb_insert(unsigned long ent, unsigned long tag, unsigned long pte);
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void tsb_flush(unsigned long ent, unsigned long tag);
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void tsb_init(struct tsb *tsb, unsigned long size);
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struct tsb_config {
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struct tsb *tsb;
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unsigned long tsb_rss_limit;
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unsigned long tsb_nentries;
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unsigned long tsb_reg_val;
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unsigned long tsb_map_vaddr;
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unsigned long tsb_map_pte;
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};
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#define MM_TSB_BASE 0
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#if defined(CONFIG_HUGETLB_PAGE) || defined(CONFIG_TRANSPARENT_HUGEPAGE)
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#define MM_TSB_HUGE 1
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#define MM_NUM_TSBS 2
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#else
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#define MM_NUM_TSBS 1
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#endif
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/* ADI tags are stored when a page is swapped out and the storage for
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* tags is allocated dynamically. There is a tag storage descriptor
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* associated with each set of tag storage pages. Tag storage descriptors
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* are allocated dynamically. Since kernel will allocate a full page for
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* each tag storage descriptor, we can store up to
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* PAGE_SIZE/sizeof(tag storage descriptor) descriptors on that page.
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*/
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typedef struct {
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unsigned long start; /* Start address for this tag storage */
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unsigned long end; /* Last address for tag storage */
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unsigned char *tags; /* Where the tags are */
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unsigned long tag_users; /* number of references to descriptor */
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} tag_storage_desc_t;
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typedef struct {
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spinlock_t lock;
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unsigned long sparc64_ctx_val;
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unsigned long hugetlb_pte_count;
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unsigned long thp_pte_count;
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struct tsb_config tsb_block[MM_NUM_TSBS];
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struct hv_tsb_descr tsb_descr[MM_NUM_TSBS];
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void *vdso;
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bool adi;
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tag_storage_desc_t *tag_store;
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spinlock_t tag_lock;
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} mm_context_t;
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#endif /* !__ASSEMBLY__ */
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#define TSB_CONFIG_TSB 0x00
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#define TSB_CONFIG_RSS_LIMIT 0x08
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#define TSB_CONFIG_NENTRIES 0x10
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#define TSB_CONFIG_REG_VAL 0x18
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#define TSB_CONFIG_MAP_VADDR 0x20
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#define TSB_CONFIG_MAP_PTE 0x28
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#endif /* __MMU_H */
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