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https://github.com/AuxXxilium/linux_dsm_epyc7002.git
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cd59f13823
Add the LPASS header files for ipq806x SOC. This includes the register definitions for the ipq806x LPAIF, and the structure definition for the driver data. Signed-off-by: Kenneth Westfield <kwestfie@codeaurora.org> Acked-by: Banajit Goswami <bgoswami@codeaurora.org> Signed-off-by: Mark Brown <broonie@kernel.org>
173 lines
6.6 KiB
C
173 lines
6.6 KiB
C
/*
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* Copyright (c) 2010-2011,2013-2015 The Linux Foundation. All rights reserved.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 and
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* only version 2 as published by the Free Software Foundation.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* lpass-lpaif-ipq806x.h -- Definitions for the QTi LPAIF in the ipq806x LPASS
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*/
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#ifndef __LPASS_LPAIF_H__
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#define __LPASS_LPAIF_H__
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#define LPAIF_BANK_OFFSET 0x1000
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/* LPAIF I2S */
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#define LPAIF_I2SCTL_REG_BASE 0x0010
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#define LPAIF_I2SCTL_REG_STRIDE 0x4
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#define LPAIF_I2SCTL_REG_ADDR(addr, port) \
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(LPAIF_I2SCTL_REG_BASE + (addr) + (LPAIF_I2SCTL_REG_STRIDE * (port)))
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enum lpaif_i2s_ports {
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LPAIF_I2S_PORT_MIN = 0,
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LPAIF_I2S_PORT_CODEC_SPK = 0,
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LPAIF_I2S_PORT_CODEC_MIC = 1,
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LPAIF_I2S_PORT_SEC_SPK = 2,
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LPAIF_I2S_PORT_SEC_MIC = 3,
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LPAIF_I2S_PORT_MI2S = 4,
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LPAIF_I2S_PORT_MAX = 4,
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LPAIF_I2S_PORT_NUM = 5,
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};
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#define LPAIF_I2SCTL_REG(port) LPAIF_I2SCTL_REG_ADDR(0x0, (port))
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#define LPAIF_I2SCTL_LOOPBACK_MASK 0x8000
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#define LPAIF_I2SCTL_LOOPBACK_SHIFT 15
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#define LPAIF_I2SCTL_LOOPBACK_DISABLE (0 << LPAIF_I2SCTL_LOOPBACK_SHIFT)
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#define LPAIF_I2SCTL_LOOPBACK_ENABLE (1 << LPAIF_I2SCTL_LOOPBACK_SHIFT)
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#define LPAIF_I2SCTL_SPKEN_MASK 0x4000
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#define LPAIF_I2SCTL_SPKEN_SHIFT 14
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#define LPAIF_I2SCTL_SPKEN_DISABLE (0 << LPAIF_I2SCTL_SPKEN_SHIFT)
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#define LPAIF_I2SCTL_SPKEN_ENABLE (1 << LPAIF_I2SCTL_SPKEN_SHIFT)
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#define LPAIF_I2SCTL_SPKMODE_MASK 0x3C00
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#define LPAIF_I2SCTL_SPKMODE_SHIFT 10
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#define LPAIF_I2SCTL_SPKMODE_NONE (0 << LPAIF_I2SCTL_SPKMODE_SHIFT)
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#define LPAIF_I2SCTL_SPKMODE_SD0 (1 << LPAIF_I2SCTL_SPKMODE_SHIFT)
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#define LPAIF_I2SCTL_SPKMODE_SD1 (2 << LPAIF_I2SCTL_SPKMODE_SHIFT)
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#define LPAIF_I2SCTL_SPKMODE_SD2 (3 << LPAIF_I2SCTL_SPKMODE_SHIFT)
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#define LPAIF_I2SCTL_SPKMODE_SD3 (4 << LPAIF_I2SCTL_SPKMODE_SHIFT)
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#define LPAIF_I2SCTL_SPKMODE_QUAD01 (5 << LPAIF_I2SCTL_SPKMODE_SHIFT)
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#define LPAIF_I2SCTL_SPKMODE_QUAD23 (6 << LPAIF_I2SCTL_SPKMODE_SHIFT)
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#define LPAIF_I2SCTL_SPKMODE_6CH (7 << LPAIF_I2SCTL_SPKMODE_SHIFT)
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#define LPAIF_I2SCTL_SPKMODE_8CH (8 << LPAIF_I2SCTL_SPKMODE_SHIFT)
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#define LPAIF_I2SCTL_SPKMONO_MASK 0x0200
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#define LPAIF_I2SCTL_SPKMONO_SHIFT 9
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#define LPAIF_I2SCTL_SPKMONO_STEREO (0 << LPAIF_I2SCTL_SPKMONO_SHIFT)
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#define LPAIF_I2SCTL_SPKMONO_MONO (1 << LPAIF_I2SCTL_SPKMONO_SHIFT)
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#define LPAIF_I2SCTL_WSSRC_MASK 0x0004
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#define LPAIF_I2SCTL_WSSRC_SHIFT 2
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#define LPAIF_I2SCTL_WSSRC_INTERNAL (0 << LPAIF_I2SCTL_WSSRC_SHIFT)
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#define LPAIF_I2SCTL_WSSRC_EXTERNAL (1 << LPAIF_I2SCTL_WSSRC_SHIFT)
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#define LPAIF_I2SCTL_BITWIDTH_MASK 0x0003
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#define LPAIF_I2SCTL_BITWIDTH_SHIFT 0
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#define LPAIF_I2SCTL_BITWIDTH_16 (0 << LPAIF_I2SCTL_BITWIDTH_SHIFT)
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#define LPAIF_I2SCTL_BITWIDTH_24 (1 << LPAIF_I2SCTL_BITWIDTH_SHIFT)
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#define LPAIF_I2SCTL_BITWIDTH_32 (2 << LPAIF_I2SCTL_BITWIDTH_SHIFT)
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/* LPAIF IRQ */
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#define LPAIF_IRQ_REG_BASE 0x3000
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#define LPAIF_IRQ_REG_STRIDE 0x1000
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#define LPAIF_IRQ_REG_ADDR(addr, port) \
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(LPAIF_IRQ_REG_BASE + (addr) + (LPAIF_IRQ_REG_STRIDE * (port)))
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enum lpaif_irq_ports {
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LPAIF_IRQ_PORT_MIN = 0,
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LPAIF_IRQ_PORT_HOST = 0,
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LPAIF_IRQ_PORT_ADSP = 1,
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LPAIF_IRQ_PORT_MAX = 2,
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LPAIF_IRQ_PORT_NUM = 3,
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};
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#define LPAIF_IRQEN_REG(port) LPAIF_IRQ_REG_ADDR(0x0, (port))
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#define LPAIF_IRQSTAT_REG(port) LPAIF_IRQ_REG_ADDR(0x4, (port))
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#define LPAIF_IRQCLEAR_REG(port) LPAIF_IRQ_REG_ADDR(0xC, (port))
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#define LPAIF_IRQ_BITSTRIDE 3
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#define LPAIF_IRQ_PER(chan) (1 << (LPAIF_IRQ_BITSTRIDE * (chan)))
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#define LPAIF_IRQ_XRUN(chan) (2 << (LPAIF_IRQ_BITSTRIDE * (chan)))
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#define LPAIF_IRQ_ERR(chan) (4 << (LPAIF_IRQ_BITSTRIDE * (chan)))
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#define LPAIF_IRQ_ALL(chan) (7 << (LPAIF_IRQ_BITSTRIDE * (chan)))
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/* LPAIF DMA */
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#define LPAIF_RDMA_REG_BASE 0x6000
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#define LPAIF_RDMA_REG_STRIDE 0x1000
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#define LPAIF_RDMA_REG_ADDR(addr, chan) \
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(LPAIF_RDMA_REG_BASE + (addr) + (LPAIF_RDMA_REG_STRIDE * (chan)))
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enum lpaif_dma_channels {
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LPAIF_RDMA_CHAN_MIN = 0,
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LPAIF_RDMA_CHAN_MI2S = 0,
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LPAIF_RDMA_CHAN_PCM0 = 1,
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LPAIF_RDMA_CHAN_PCM1 = 2,
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LPAIF_RDMA_CHAN_MAX = 4,
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LPAIF_RDMA_CHAN_NUM = 5,
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};
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#define LPAIF_RDMACTL_REG(chan) LPAIF_RDMA_REG_ADDR(0x00, (chan))
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#define LPAIF_RDMABASE_REG(chan) LPAIF_RDMA_REG_ADDR(0x04, (chan))
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#define LPAIF_RDMABUFF_REG(chan) LPAIF_RDMA_REG_ADDR(0x08, (chan))
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#define LPAIF_RDMACURR_REG(chan) LPAIF_RDMA_REG_ADDR(0x0C, (chan))
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#define LPAIF_RDMAPER_REG(chan) LPAIF_RDMA_REG_ADDR(0x10, (chan))
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#define LPAIF_RDMACTL_BURSTEN_MASK 0x800
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#define LPAIF_RDMACTL_BURSTEN_SHIFT 11
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#define LPAIF_RDMACTL_BURSTEN_SINGLE (0 << LPAIF_RDMACTL_BURSTEN_SHIFT)
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#define LPAIF_RDMACTL_BURSTEN_INCR4 (1 << LPAIF_RDMACTL_BURSTEN_SHIFT)
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#define LPAIF_RDMACTL_WPSCNT_MASK 0x700
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#define LPAIF_RDMACTL_WPSCNT_SHIFT 8
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#define LPAIF_RDMACTL_WPSCNT_ONE (0 << LPAIF_RDMACTL_WPSCNT_SHIFT)
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#define LPAIF_RDMACTL_WPSCNT_TWO (1 << LPAIF_RDMACTL_WPSCNT_SHIFT)
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#define LPAIF_RDMACTL_WPSCNT_THREE (2 << LPAIF_RDMACTL_WPSCNT_SHIFT)
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#define LPAIF_RDMACTL_WPSCNT_FOUR (3 << LPAIF_RDMACTL_WPSCNT_SHIFT)
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#define LPAIF_RDMACTL_WPSCNT_SIX (5 << LPAIF_RDMACTL_WPSCNT_SHIFT)
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#define LPAIF_RDMACTL_WPSCNT_EIGHT (7 << LPAIF_RDMACTL_WPSCNT_SHIFT)
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#define LPAIF_RDMACTL_AUDINTF_MASK 0x0F0
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#define LPAIF_RDMACTL_AUDINTF_SHIFT 4
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#define LPAIF_RDMACTL_AUDINTF_NONE (0 << LPAIF_RDMACTL_AUDINTF_SHIFT)
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#define LPAIF_RDMACTL_AUDINTF_CODEC (1 << LPAIF_RDMACTL_AUDINTF_SHIFT)
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#define LPAIF_RDMACTL_AUDINTF_PCM (2 << LPAIF_RDMACTL_AUDINTF_SHIFT)
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#define LPAIF_RDMACTL_AUDINTF_SEC_I2S (3 << LPAIF_RDMACTL_AUDINTF_SHIFT)
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#define LPAIF_RDMACTL_AUDINTF_MI2S (4 << LPAIF_RDMACTL_AUDINTF_SHIFT)
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#define LPAIF_RDMACTL_AUDINTF_HDMI (5 << LPAIF_RDMACTL_AUDINTF_SHIFT)
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#define LPAIF_RDMACTL_AUDINTF_SEC_PCM (7 << LPAIF_RDMACTL_AUDINTF_SHIFT)
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#define LPAIF_RDMACTL_FIFOWM_MASK 0x00E
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#define LPAIF_RDMACTL_FIFOWM_SHIFT 1
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#define LPAIF_RDMACTL_FIFOWM_1 (0 << LPAIF_RDMACTL_FIFOWM_SHIFT)
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#define LPAIF_RDMACTL_FIFOWM_2 (1 << LPAIF_RDMACTL_FIFOWM_SHIFT)
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#define LPAIF_RDMACTL_FIFOWM_3 (2 << LPAIF_RDMACTL_FIFOWM_SHIFT)
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#define LPAIF_RDMACTL_FIFOWM_4 (3 << LPAIF_RDMACTL_FIFOWM_SHIFT)
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#define LPAIF_RDMACTL_FIFOWM_5 (4 << LPAIF_RDMACTL_FIFOWM_SHIFT)
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#define LPAIF_RDMACTL_FIFOWM_6 (5 << LPAIF_RDMACTL_FIFOWM_SHIFT)
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#define LPAIF_RDMACTL_FIFOWM_7 (6 << LPAIF_RDMACTL_FIFOWM_SHIFT)
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#define LPAIF_RDMACTL_FIFOWM_8 (7 << LPAIF_RDMACTL_FIFOWM_SHIFT)
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#define LPAIF_RDMACTL_ENABLE_MASK 0x1
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#define LPAIF_RDMACTL_ENABLE_SHIFT 0
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#define LPAIF_RDMACTL_ENABLE_OFF (0 << LPAIF_RDMACTL_ENABLE_SHIFT)
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#define LPAIF_RDMACTL_ENABLE_ON (1 << LPAIF_RDMACTL_ENABLE_SHIFT)
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#endif /* __LPASS_LPAIF_H__ */
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