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8d1cf34e7a
This patch tweaks the way some PTE bit combinations are defined, in such a way that the 32 and 64-bit variant become almost identical and that will make it easier to bring in a new common pte-* file for the new variant of the Book3-E support. The combination of bits defining access to kernel pages are now clearly separated from the combination used by userspace and the core VM. The resulting generated code should remain identical unless I made a mistake. Note: While at it, I removed a non-sensical statement related to CONFIG_KGDB in ppc_mmu_32.c which could cause kernel mappings to be user accessible when that option is enabled. Probably something that bitrot. Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
275 lines
7.9 KiB
C
275 lines
7.9 KiB
C
/*
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* This file contains the routines for handling the MMU on those
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* PowerPC implementations where the MMU substantially follows the
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* architecture specification. This includes the 6xx, 7xx, 7xxx,
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* 8260, and POWER3 implementations but excludes the 8xx and 4xx.
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* -- paulus
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*
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* Derived from arch/ppc/mm/init.c:
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* Copyright (C) 1995-1996 Gary Thomas (gdt@linuxppc.org)
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*
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* Modifications by Paul Mackerras (PowerMac) (paulus@cs.anu.edu.au)
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* and Cort Dougan (PReP) (cort@cs.nmt.edu)
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* Copyright (C) 1996 Paul Mackerras
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*
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* Derived from "arch/i386/mm/init.c"
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* Copyright (C) 1991, 1992, 1993, 1994 Linus Torvalds
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License
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* as published by the Free Software Foundation; either version
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* 2 of the License, or (at your option) any later version.
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*
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*/
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#include <linux/kernel.h>
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#include <linux/mm.h>
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#include <linux/init.h>
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#include <linux/highmem.h>
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#include <linux/lmb.h>
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#include <asm/prom.h>
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#include <asm/mmu.h>
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#include <asm/machdep.h>
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#include "mmu_decl.h"
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struct hash_pte *Hash, *Hash_end;
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unsigned long Hash_size, Hash_mask;
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unsigned long _SDR1;
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struct ppc_bat BATS[8][2]; /* 8 pairs of IBAT, DBAT */
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struct batrange { /* stores address ranges mapped by BATs */
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unsigned long start;
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unsigned long limit;
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phys_addr_t phys;
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} bat_addrs[8];
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/*
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* Return PA for this VA if it is mapped by a BAT, or 0
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*/
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phys_addr_t v_mapped_by_bats(unsigned long va)
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{
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int b;
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for (b = 0; b < 4; ++b)
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if (va >= bat_addrs[b].start && va < bat_addrs[b].limit)
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return bat_addrs[b].phys + (va - bat_addrs[b].start);
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return 0;
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}
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/*
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* Return VA for a given PA or 0 if not mapped
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*/
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unsigned long p_mapped_by_bats(phys_addr_t pa)
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{
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int b;
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for (b = 0; b < 4; ++b)
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if (pa >= bat_addrs[b].phys
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&& pa < (bat_addrs[b].limit-bat_addrs[b].start)
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+bat_addrs[b].phys)
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return bat_addrs[b].start+(pa-bat_addrs[b].phys);
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return 0;
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}
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unsigned long __init mmu_mapin_ram(void)
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{
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unsigned long tot, bl, done;
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unsigned long max_size = (256<<20);
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if (__map_without_bats) {
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printk(KERN_DEBUG "RAM mapped without BATs\n");
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return 0;
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}
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/* Set up BAT2 and if necessary BAT3 to cover RAM. */
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/* Make sure we don't map a block larger than the
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smallest alignment of the physical address. */
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tot = total_lowmem;
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for (bl = 128<<10; bl < max_size; bl <<= 1) {
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if (bl * 2 > tot)
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break;
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}
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setbat(2, PAGE_OFFSET, 0, bl, PAGE_KERNEL_X);
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done = (unsigned long)bat_addrs[2].limit - PAGE_OFFSET + 1;
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if ((done < tot) && !bat_addrs[3].limit) {
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/* use BAT3 to cover a bit more */
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tot -= done;
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for (bl = 128<<10; bl < max_size; bl <<= 1)
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if (bl * 2 > tot)
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break;
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setbat(3, PAGE_OFFSET+done, done, bl, PAGE_KERNEL_X);
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done = (unsigned long)bat_addrs[3].limit - PAGE_OFFSET + 1;
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}
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return done;
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}
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/*
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* Set up one of the I/D BAT (block address translation) register pairs.
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* The parameters are not checked; in particular size must be a power
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* of 2 between 128k and 256M.
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*/
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void __init setbat(int index, unsigned long virt, phys_addr_t phys,
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unsigned int size, int flags)
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{
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unsigned int bl;
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int wimgxpp;
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struct ppc_bat *bat = BATS[index];
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if ((flags & _PAGE_NO_CACHE) ||
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(cpu_has_feature(CPU_FTR_NEED_COHERENT) == 0))
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flags &= ~_PAGE_COHERENT;
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bl = (size >> 17) - 1;
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if (PVR_VER(mfspr(SPRN_PVR)) != 1) {
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/* 603, 604, etc. */
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/* Do DBAT first */
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wimgxpp = flags & (_PAGE_WRITETHRU | _PAGE_NO_CACHE
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| _PAGE_COHERENT | _PAGE_GUARDED);
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wimgxpp |= (flags & _PAGE_RW)? BPP_RW: BPP_RX;
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bat[1].batu = virt | (bl << 2) | 2; /* Vs=1, Vp=0 */
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bat[1].batl = BAT_PHYS_ADDR(phys) | wimgxpp;
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if (flags & _PAGE_USER)
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bat[1].batu |= 1; /* Vp = 1 */
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if (flags & _PAGE_GUARDED) {
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/* G bit must be zero in IBATs */
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bat[0].batu = bat[0].batl = 0;
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} else {
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/* make IBAT same as DBAT */
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bat[0] = bat[1];
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}
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} else {
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/* 601 cpu */
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if (bl > BL_8M)
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bl = BL_8M;
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wimgxpp = flags & (_PAGE_WRITETHRU | _PAGE_NO_CACHE
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| _PAGE_COHERENT);
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wimgxpp |= (flags & _PAGE_RW)?
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((flags & _PAGE_USER)? PP_RWRW: PP_RWXX): PP_RXRX;
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bat->batu = virt | wimgxpp | 4; /* Ks=0, Ku=1 */
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bat->batl = phys | bl | 0x40; /* V=1 */
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}
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bat_addrs[index].start = virt;
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bat_addrs[index].limit = virt + ((bl + 1) << 17) - 1;
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bat_addrs[index].phys = phys;
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}
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/*
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* Preload a translation in the hash table
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*/
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void hash_preload(struct mm_struct *mm, unsigned long ea,
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unsigned long access, unsigned long trap)
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{
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pmd_t *pmd;
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if (Hash == 0)
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return;
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pmd = pmd_offset(pud_offset(pgd_offset(mm, ea), ea), ea);
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if (!pmd_none(*pmd))
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add_hash_page(mm->context.id, ea, pmd_val(*pmd));
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}
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/*
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* Initialize the hash table and patch the instructions in hashtable.S.
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*/
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void __init MMU_init_hw(void)
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{
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unsigned int hmask, mb, mb2;
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unsigned int n_hpteg, lg_n_hpteg;
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extern unsigned int hash_page_patch_A[];
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extern unsigned int hash_page_patch_B[], hash_page_patch_C[];
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extern unsigned int hash_page[];
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extern unsigned int flush_hash_patch_A[], flush_hash_patch_B[];
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if (!mmu_has_feature(MMU_FTR_HPTE_TABLE)) {
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/*
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* Put a blr (procedure return) instruction at the
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* start of hash_page, since we can still get DSI
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* exceptions on a 603.
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*/
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hash_page[0] = 0x4e800020;
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flush_icache_range((unsigned long) &hash_page[0],
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(unsigned long) &hash_page[1]);
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return;
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}
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if ( ppc_md.progress ) ppc_md.progress("hash:enter", 0x105);
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#define LG_HPTEG_SIZE 6 /* 64 bytes per HPTEG */
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#define SDR1_LOW_BITS ((n_hpteg - 1) >> 10)
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#define MIN_N_HPTEG 1024 /* min 64kB hash table */
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/*
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* Allow 1 HPTE (1/8 HPTEG) for each page of memory.
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* This is less than the recommended amount, but then
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* Linux ain't AIX.
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*/
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n_hpteg = total_memory / (PAGE_SIZE * 8);
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if (n_hpteg < MIN_N_HPTEG)
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n_hpteg = MIN_N_HPTEG;
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lg_n_hpteg = __ilog2(n_hpteg);
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if (n_hpteg & (n_hpteg - 1)) {
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++lg_n_hpteg; /* round up if not power of 2 */
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n_hpteg = 1 << lg_n_hpteg;
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}
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Hash_size = n_hpteg << LG_HPTEG_SIZE;
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/*
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* Find some memory for the hash table.
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*/
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if ( ppc_md.progress ) ppc_md.progress("hash:find piece", 0x322);
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Hash = __va(lmb_alloc_base(Hash_size, Hash_size,
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__initial_memory_limit_addr));
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cacheable_memzero(Hash, Hash_size);
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_SDR1 = __pa(Hash) | SDR1_LOW_BITS;
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Hash_end = (struct hash_pte *) ((unsigned long)Hash + Hash_size);
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printk("Total memory = %lldMB; using %ldkB for hash table (at %p)\n",
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(unsigned long long)(total_memory >> 20), Hash_size >> 10, Hash);
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/*
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* Patch up the instructions in hashtable.S:create_hpte
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*/
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if ( ppc_md.progress ) ppc_md.progress("hash:patch", 0x345);
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Hash_mask = n_hpteg - 1;
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hmask = Hash_mask >> (16 - LG_HPTEG_SIZE);
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mb2 = mb = 32 - LG_HPTEG_SIZE - lg_n_hpteg;
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if (lg_n_hpteg > 16)
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mb2 = 16 - LG_HPTEG_SIZE;
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hash_page_patch_A[0] = (hash_page_patch_A[0] & ~0xffff)
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| ((unsigned int)(Hash) >> 16);
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hash_page_patch_A[1] = (hash_page_patch_A[1] & ~0x7c0) | (mb << 6);
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hash_page_patch_A[2] = (hash_page_patch_A[2] & ~0x7c0) | (mb2 << 6);
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hash_page_patch_B[0] = (hash_page_patch_B[0] & ~0xffff) | hmask;
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hash_page_patch_C[0] = (hash_page_patch_C[0] & ~0xffff) | hmask;
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/*
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* Ensure that the locations we've patched have been written
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* out from the data cache and invalidated in the instruction
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* cache, on those machines with split caches.
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*/
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flush_icache_range((unsigned long) &hash_page_patch_A[0],
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(unsigned long) &hash_page_patch_C[1]);
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/*
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* Patch up the instructions in hashtable.S:flush_hash_page
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*/
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flush_hash_patch_A[0] = (flush_hash_patch_A[0] & ~0xffff)
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| ((unsigned int)(Hash) >> 16);
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flush_hash_patch_A[1] = (flush_hash_patch_A[1] & ~0x7c0) | (mb << 6);
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flush_hash_patch_A[2] = (flush_hash_patch_A[2] & ~0x7c0) | (mb2 << 6);
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flush_hash_patch_B[0] = (flush_hash_patch_B[0] & ~0xffff) | hmask;
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flush_icache_range((unsigned long) &flush_hash_patch_A[0],
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(unsigned long) &flush_hash_patch_B[1]);
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if ( ppc_md.progress ) ppc_md.progress("hash:done", 0x205);
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}
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