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https://github.com/AuxXxilium/linux_dsm_epyc7002.git
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733b8bc183
Complement commit 102cedc32a ("MIPS: microMIPS: Floating point
support.") which introduced microMIPS FPU emulation, but did not adjust
the encoding of the BREAK instruction used to terminate the branch delay
slot emulation frame. Consequently the execution of any such frame is
indeterminate and, depending on CPU configuration, will result in random
code execution or an offending program being terminated with SIGILL.
This is because the regular MIPS BREAK instruction is encoded with the 0
major and the 0xd minor opcode, however in the microMIPS instruction set
this major/minor opcode pair denotes an encoding reserved for the DSP
ASE. Instead the microMIPS BREAK instruction is encoded with the 0
major and the 0x7 minor opcode.
Use the correct BREAK encoding for microMIPS FPU emulation then.
Signed-off-by: Maciej W. Rozycki <macro@imgtec.com>
Cc: Aurelien Jarno <aurelien@aurel32.net>
Cc: linux-mips@linux-mips.org
Patchwork: https://patchwork.linux-mips.org/patch/12174/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
96 lines
2.9 KiB
C
96 lines
2.9 KiB
C
/*
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* This program is free software; you can distribute it and/or modify it
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* under the terms of the GNU General Public License (Version 2) as
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* published by the Free Software Foundation.
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*
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* This program is distributed in the hope it will be useful, but WITHOUT
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
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* for more details.
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*
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* You should have received a copy of the GNU General Public License along
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* with this program; if not, write to the Free Software Foundation, Inc.,
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* 59 Temple Place - Suite 330, Boston MA 02111-1307, USA.
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*
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* Further private data for which no space exists in mips_fpu_struct.
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* This should be subsumed into the mips_fpu_struct structure as
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* defined in processor.h as soon as the absurd wired absolute assembler
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* offsets become dynamic at compile time.
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*
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* Kevin D. Kissell, kevink@mips.com and Carsten Langgaard, carstenl@mips.com
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* Copyright (C) 2000 MIPS Technologies, Inc. All rights reserved.
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*/
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#ifndef _ASM_FPU_EMULATOR_H
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#define _ASM_FPU_EMULATOR_H
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#include <linux/sched.h>
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#include <asm/break.h>
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#include <asm/thread_info.h>
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#include <asm/inst.h>
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#include <asm/local.h>
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#include <asm/processor.h>
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#ifdef CONFIG_DEBUG_FS
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struct mips_fpu_emulator_stats {
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unsigned long emulated;
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unsigned long loads;
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unsigned long stores;
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unsigned long cp1ops;
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unsigned long cp1xops;
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unsigned long errors;
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unsigned long ieee754_inexact;
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unsigned long ieee754_underflow;
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unsigned long ieee754_overflow;
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unsigned long ieee754_zerodiv;
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unsigned long ieee754_invalidop;
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unsigned long ds_emul;
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};
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DECLARE_PER_CPU(struct mips_fpu_emulator_stats, fpuemustats);
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#define MIPS_FPU_EMU_INC_STATS(M) \
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do { \
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preempt_disable(); \
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__this_cpu_inc(fpuemustats.M); \
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preempt_enable(); \
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} while (0)
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#else
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#define MIPS_FPU_EMU_INC_STATS(M) do { } while (0)
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#endif /* CONFIG_DEBUG_FS */
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extern int mips_dsemul(struct pt_regs *regs, mips_instruction ir,
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unsigned long cpc);
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extern int do_dsemulret(struct pt_regs *xcp);
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extern int fpu_emulator_cop1Handler(struct pt_regs *xcp,
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struct mips_fpu_struct *ctx, int has_fpu,
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void *__user *fault_addr);
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int process_fpemu_return(int sig, void __user *fault_addr,
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unsigned long fcr31);
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int mm_isBranchInstr(struct pt_regs *regs, struct mm_decoded_insn dec_insn,
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unsigned long *contpc);
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/*
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* Instruction inserted following the badinst to further tag the sequence
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*/
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#define BD_COOKIE 0x0000bd36 /* tne $0, $0 with baggage */
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/*
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* Break instruction with special math emu break code set
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*/
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#define BREAK_MATH(micromips) (((micromips) ? 0x7 : 0xd) | (BRK_MEMU << 16))
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#define SIGNALLING_NAN 0x7ff800007ff80000LL
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static inline void fpu_emulator_init_fpu(void)
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{
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struct task_struct *t = current;
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int i;
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for (i = 0; i < 32; i++)
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set_fpr64(&t->thread.fpu.fpr[i], 0, SIGNALLING_NAN);
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}
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#endif /* _ASM_FPU_EMULATOR_H */
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