mirror of
https://github.com/AuxXxilium/linux_dsm_epyc7002.git
synced 2024-12-05 13:16:39 +07:00
8ad165e922
The driver handles wakeup irq correctly using device_init_wakeup and enable_irq_wake. There's no need to use IRQF_NO_SUSPEND while registering the interrupt. This patch removes the use of IRQF_NO_SUSPEND flag. Signed-off-by: Sudeep Holla <sudeep.holla@arm.com> Acked-by: Thierry Reding <treding@nvidia.com> Acked-by: Laxman Dewangan <ldewangan@nvidia.com> Signed-off-by: Dmitry Torokhov <dmitry.torokhov@gmail.com>
836 lines
21 KiB
C
836 lines
21 KiB
C
/*
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* Keyboard class input driver for the NVIDIA Tegra SoC internal matrix
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* keyboard controller
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*
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* Copyright (c) 2009-2011, NVIDIA Corporation.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful, but WITHOUT
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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* more details.
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*
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* You should have received a copy of the GNU General Public License along
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* with this program; if not, write to the Free Software Foundation, Inc.,
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* 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
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*/
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#include <linux/kernel.h>
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#include <linux/module.h>
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#include <linux/input.h>
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#include <linux/platform_device.h>
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#include <linux/delay.h>
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#include <linux/io.h>
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#include <linux/interrupt.h>
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#include <linux/of.h>
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#include <linux/of_device.h>
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#include <linux/clk.h>
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#include <linux/slab.h>
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#include <linux/input/matrix_keypad.h>
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#include <linux/reset.h>
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#include <linux/err.h>
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#define KBC_MAX_KPENT 8
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/* Maximum row/column supported by Tegra KBC yet is 16x8 */
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#define KBC_MAX_GPIO 24
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/* Maximum keys supported by Tegra KBC yet is 16 x 8*/
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#define KBC_MAX_KEY (16 * 8)
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#define KBC_MAX_DEBOUNCE_CNT 0x3ffu
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/* KBC row scan time and delay for beginning the row scan. */
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#define KBC_ROW_SCAN_TIME 16
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#define KBC_ROW_SCAN_DLY 5
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/* KBC uses a 32KHz clock so a cycle = 1/32Khz */
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#define KBC_CYCLE_MS 32
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/* KBC Registers */
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/* KBC Control Register */
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#define KBC_CONTROL_0 0x0
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#define KBC_FIFO_TH_CNT_SHIFT(cnt) (cnt << 14)
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#define KBC_DEBOUNCE_CNT_SHIFT(cnt) (cnt << 4)
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#define KBC_CONTROL_FIFO_CNT_INT_EN (1 << 3)
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#define KBC_CONTROL_KEYPRESS_INT_EN (1 << 1)
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#define KBC_CONTROL_KBC_EN (1 << 0)
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/* KBC Interrupt Register */
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#define KBC_INT_0 0x4
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#define KBC_INT_FIFO_CNT_INT_STATUS (1 << 2)
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#define KBC_INT_KEYPRESS_INT_STATUS (1 << 0)
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#define KBC_ROW_CFG0_0 0x8
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#define KBC_COL_CFG0_0 0x18
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#define KBC_TO_CNT_0 0x24
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#define KBC_INIT_DLY_0 0x28
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#define KBC_RPT_DLY_0 0x2c
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#define KBC_KP_ENT0_0 0x30
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#define KBC_KP_ENT1_0 0x34
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#define KBC_ROW0_MASK_0 0x38
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#define KBC_ROW_SHIFT 3
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enum tegra_pin_type {
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PIN_CFG_IGNORE,
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PIN_CFG_COL,
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PIN_CFG_ROW,
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};
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/* Tegra KBC hw support */
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struct tegra_kbc_hw_support {
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int max_rows;
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int max_columns;
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};
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struct tegra_kbc_pin_cfg {
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enum tegra_pin_type type;
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unsigned char num;
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};
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struct tegra_kbc {
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struct device *dev;
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unsigned int debounce_cnt;
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unsigned int repeat_cnt;
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struct tegra_kbc_pin_cfg pin_cfg[KBC_MAX_GPIO];
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const struct matrix_keymap_data *keymap_data;
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bool wakeup;
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void __iomem *mmio;
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struct input_dev *idev;
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int irq;
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spinlock_t lock;
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unsigned int repoll_dly;
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unsigned long cp_dly_jiffies;
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unsigned int cp_to_wkup_dly;
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bool use_fn_map;
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bool use_ghost_filter;
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bool keypress_caused_wake;
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unsigned short keycode[KBC_MAX_KEY * 2];
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unsigned short current_keys[KBC_MAX_KPENT];
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unsigned int num_pressed_keys;
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u32 wakeup_key;
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struct timer_list timer;
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struct clk *clk;
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struct reset_control *rst;
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const struct tegra_kbc_hw_support *hw_support;
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int max_keys;
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int num_rows_and_columns;
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};
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static void tegra_kbc_report_released_keys(struct input_dev *input,
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unsigned short old_keycodes[],
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unsigned int old_num_keys,
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unsigned short new_keycodes[],
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unsigned int new_num_keys)
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{
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unsigned int i, j;
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for (i = 0; i < old_num_keys; i++) {
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for (j = 0; j < new_num_keys; j++)
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if (old_keycodes[i] == new_keycodes[j])
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break;
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if (j == new_num_keys)
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input_report_key(input, old_keycodes[i], 0);
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}
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}
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static void tegra_kbc_report_pressed_keys(struct input_dev *input,
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unsigned char scancodes[],
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unsigned short keycodes[],
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unsigned int num_pressed_keys)
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{
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unsigned int i;
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for (i = 0; i < num_pressed_keys; i++) {
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input_event(input, EV_MSC, MSC_SCAN, scancodes[i]);
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input_report_key(input, keycodes[i], 1);
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}
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}
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static void tegra_kbc_report_keys(struct tegra_kbc *kbc)
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{
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unsigned char scancodes[KBC_MAX_KPENT];
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unsigned short keycodes[KBC_MAX_KPENT];
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u32 val = 0;
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unsigned int i;
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unsigned int num_down = 0;
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bool fn_keypress = false;
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bool key_in_same_row = false;
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bool key_in_same_col = false;
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for (i = 0; i < KBC_MAX_KPENT; i++) {
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if ((i % 4) == 0)
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val = readl(kbc->mmio + KBC_KP_ENT0_0 + i);
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if (val & 0x80) {
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unsigned int col = val & 0x07;
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unsigned int row = (val >> 3) & 0x0f;
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unsigned char scancode =
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MATRIX_SCAN_CODE(row, col, KBC_ROW_SHIFT);
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scancodes[num_down] = scancode;
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keycodes[num_down] = kbc->keycode[scancode];
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/* If driver uses Fn map, do not report the Fn key. */
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if ((keycodes[num_down] == KEY_FN) && kbc->use_fn_map)
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fn_keypress = true;
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else
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num_down++;
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}
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val >>= 8;
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}
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/*
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* Matrix keyboard designs are prone to keyboard ghosting.
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* Ghosting occurs if there are 3 keys such that -
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* any 2 of the 3 keys share a row, and any 2 of them share a column.
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* If so ignore the key presses for this iteration.
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*/
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if (kbc->use_ghost_filter && num_down >= 3) {
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for (i = 0; i < num_down; i++) {
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unsigned int j;
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u8 curr_col = scancodes[i] & 0x07;
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u8 curr_row = scancodes[i] >> KBC_ROW_SHIFT;
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/*
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* Find 2 keys such that one key is in the same row
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* and the other is in the same column as the i-th key.
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*/
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for (j = i + 1; j < num_down; j++) {
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u8 col = scancodes[j] & 0x07;
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u8 row = scancodes[j] >> KBC_ROW_SHIFT;
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if (col == curr_col)
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key_in_same_col = true;
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if (row == curr_row)
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key_in_same_row = true;
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}
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}
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}
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/*
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* If the platform uses Fn keymaps, translate keys on a Fn keypress.
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* Function keycodes are max_keys apart from the plain keycodes.
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*/
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if (fn_keypress) {
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for (i = 0; i < num_down; i++) {
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scancodes[i] += kbc->max_keys;
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keycodes[i] = kbc->keycode[scancodes[i]];
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}
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}
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/* Ignore the key presses for this iteration? */
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if (key_in_same_col && key_in_same_row)
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return;
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tegra_kbc_report_released_keys(kbc->idev,
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kbc->current_keys, kbc->num_pressed_keys,
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keycodes, num_down);
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tegra_kbc_report_pressed_keys(kbc->idev, scancodes, keycodes, num_down);
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input_sync(kbc->idev);
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memcpy(kbc->current_keys, keycodes, sizeof(kbc->current_keys));
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kbc->num_pressed_keys = num_down;
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}
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static void tegra_kbc_set_fifo_interrupt(struct tegra_kbc *kbc, bool enable)
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{
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u32 val;
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val = readl(kbc->mmio + KBC_CONTROL_0);
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if (enable)
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val |= KBC_CONTROL_FIFO_CNT_INT_EN;
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else
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val &= ~KBC_CONTROL_FIFO_CNT_INT_EN;
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writel(val, kbc->mmio + KBC_CONTROL_0);
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}
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static void tegra_kbc_keypress_timer(unsigned long data)
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{
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struct tegra_kbc *kbc = (struct tegra_kbc *)data;
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unsigned long flags;
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u32 val;
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unsigned int i;
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spin_lock_irqsave(&kbc->lock, flags);
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val = (readl(kbc->mmio + KBC_INT_0) >> 4) & 0xf;
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if (val) {
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unsigned long dly;
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tegra_kbc_report_keys(kbc);
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/*
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* If more than one keys are pressed we need not wait
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* for the repoll delay.
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*/
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dly = (val == 1) ? kbc->repoll_dly : 1;
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mod_timer(&kbc->timer, jiffies + msecs_to_jiffies(dly));
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} else {
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/* Release any pressed keys and exit the polling loop */
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for (i = 0; i < kbc->num_pressed_keys; i++)
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input_report_key(kbc->idev, kbc->current_keys[i], 0);
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input_sync(kbc->idev);
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kbc->num_pressed_keys = 0;
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/* All keys are released so enable the keypress interrupt */
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tegra_kbc_set_fifo_interrupt(kbc, true);
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}
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spin_unlock_irqrestore(&kbc->lock, flags);
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}
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static irqreturn_t tegra_kbc_isr(int irq, void *args)
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{
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struct tegra_kbc *kbc = args;
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unsigned long flags;
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u32 val;
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spin_lock_irqsave(&kbc->lock, flags);
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/*
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* Quickly bail out & reenable interrupts if the fifo threshold
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* count interrupt wasn't the interrupt source
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*/
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val = readl(kbc->mmio + KBC_INT_0);
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writel(val, kbc->mmio + KBC_INT_0);
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if (val & KBC_INT_FIFO_CNT_INT_STATUS) {
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/*
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* Until all keys are released, defer further processing to
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* the polling loop in tegra_kbc_keypress_timer.
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*/
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tegra_kbc_set_fifo_interrupt(kbc, false);
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mod_timer(&kbc->timer, jiffies + kbc->cp_dly_jiffies);
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} else if (val & KBC_INT_KEYPRESS_INT_STATUS) {
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/* We can be here only through system resume path */
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kbc->keypress_caused_wake = true;
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}
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spin_unlock_irqrestore(&kbc->lock, flags);
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return IRQ_HANDLED;
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}
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static void tegra_kbc_setup_wakekeys(struct tegra_kbc *kbc, bool filter)
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{
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int i;
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unsigned int rst_val;
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/* Either mask all keys or none. */
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rst_val = (filter && !kbc->wakeup) ? ~0 : 0;
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for (i = 0; i < kbc->hw_support->max_rows; i++)
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writel(rst_val, kbc->mmio + KBC_ROW0_MASK_0 + i * 4);
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}
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static void tegra_kbc_config_pins(struct tegra_kbc *kbc)
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{
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int i;
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for (i = 0; i < KBC_MAX_GPIO; i++) {
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u32 r_shft = 5 * (i % 6);
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u32 c_shft = 4 * (i % 8);
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u32 r_mask = 0x1f << r_shft;
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u32 c_mask = 0x0f << c_shft;
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u32 r_offs = (i / 6) * 4 + KBC_ROW_CFG0_0;
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u32 c_offs = (i / 8) * 4 + KBC_COL_CFG0_0;
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u32 row_cfg = readl(kbc->mmio + r_offs);
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u32 col_cfg = readl(kbc->mmio + c_offs);
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row_cfg &= ~r_mask;
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col_cfg &= ~c_mask;
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switch (kbc->pin_cfg[i].type) {
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case PIN_CFG_ROW:
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row_cfg |= ((kbc->pin_cfg[i].num << 1) | 1) << r_shft;
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break;
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case PIN_CFG_COL:
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col_cfg |= ((kbc->pin_cfg[i].num << 1) | 1) << c_shft;
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break;
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case PIN_CFG_IGNORE:
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break;
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}
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writel(row_cfg, kbc->mmio + r_offs);
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writel(col_cfg, kbc->mmio + c_offs);
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}
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}
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static int tegra_kbc_start(struct tegra_kbc *kbc)
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{
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unsigned int debounce_cnt;
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u32 val = 0;
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clk_prepare_enable(kbc->clk);
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/* Reset the KBC controller to clear all previous status.*/
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reset_control_assert(kbc->rst);
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udelay(100);
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reset_control_assert(kbc->rst);
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udelay(100);
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tegra_kbc_config_pins(kbc);
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tegra_kbc_setup_wakekeys(kbc, false);
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writel(kbc->repeat_cnt, kbc->mmio + KBC_RPT_DLY_0);
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/* Keyboard debounce count is maximum of 12 bits. */
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debounce_cnt = min(kbc->debounce_cnt, KBC_MAX_DEBOUNCE_CNT);
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val = KBC_DEBOUNCE_CNT_SHIFT(debounce_cnt);
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val |= KBC_FIFO_TH_CNT_SHIFT(1); /* set fifo interrupt threshold to 1 */
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val |= KBC_CONTROL_FIFO_CNT_INT_EN; /* interrupt on FIFO threshold */
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val |= KBC_CONTROL_KBC_EN; /* enable */
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writel(val, kbc->mmio + KBC_CONTROL_0);
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/*
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* Compute the delay(ns) from interrupt mode to continuous polling
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* mode so the timer routine is scheduled appropriately.
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*/
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val = readl(kbc->mmio + KBC_INIT_DLY_0);
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kbc->cp_dly_jiffies = usecs_to_jiffies((val & 0xfffff) * 32);
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kbc->num_pressed_keys = 0;
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/*
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* Atomically clear out any remaining entries in the key FIFO
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* and enable keyboard interrupts.
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*/
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while (1) {
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val = readl(kbc->mmio + KBC_INT_0);
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val >>= 4;
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if (!val)
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break;
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val = readl(kbc->mmio + KBC_KP_ENT0_0);
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val = readl(kbc->mmio + KBC_KP_ENT1_0);
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}
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writel(0x7, kbc->mmio + KBC_INT_0);
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enable_irq(kbc->irq);
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return 0;
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}
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static void tegra_kbc_stop(struct tegra_kbc *kbc)
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{
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unsigned long flags;
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u32 val;
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spin_lock_irqsave(&kbc->lock, flags);
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val = readl(kbc->mmio + KBC_CONTROL_0);
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val &= ~1;
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writel(val, kbc->mmio + KBC_CONTROL_0);
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spin_unlock_irqrestore(&kbc->lock, flags);
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disable_irq(kbc->irq);
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del_timer_sync(&kbc->timer);
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clk_disable_unprepare(kbc->clk);
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}
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static int tegra_kbc_open(struct input_dev *dev)
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{
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struct tegra_kbc *kbc = input_get_drvdata(dev);
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return tegra_kbc_start(kbc);
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}
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static void tegra_kbc_close(struct input_dev *dev)
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{
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struct tegra_kbc *kbc = input_get_drvdata(dev);
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return tegra_kbc_stop(kbc);
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}
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static bool tegra_kbc_check_pin_cfg(const struct tegra_kbc *kbc,
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unsigned int *num_rows)
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{
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int i;
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*num_rows = 0;
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for (i = 0; i < KBC_MAX_GPIO; i++) {
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const struct tegra_kbc_pin_cfg *pin_cfg = &kbc->pin_cfg[i];
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switch (pin_cfg->type) {
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case PIN_CFG_ROW:
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if (pin_cfg->num >= kbc->hw_support->max_rows) {
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dev_err(kbc->dev,
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"pin_cfg[%d]: invalid row number %d\n",
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i, pin_cfg->num);
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return false;
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}
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(*num_rows)++;
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break;
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case PIN_CFG_COL:
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if (pin_cfg->num >= kbc->hw_support->max_columns) {
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dev_err(kbc->dev,
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"pin_cfg[%d]: invalid column number %d\n",
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i, pin_cfg->num);
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return false;
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}
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|
break;
|
|
|
|
case PIN_CFG_IGNORE:
|
|
break;
|
|
|
|
default:
|
|
dev_err(kbc->dev,
|
|
"pin_cfg[%d]: invalid entry type %d\n",
|
|
pin_cfg->type, pin_cfg->num);
|
|
return false;
|
|
}
|
|
}
|
|
|
|
return true;
|
|
}
|
|
|
|
static int tegra_kbc_parse_dt(struct tegra_kbc *kbc)
|
|
{
|
|
struct device_node *np = kbc->dev->of_node;
|
|
u32 prop;
|
|
int i;
|
|
u32 num_rows = 0;
|
|
u32 num_cols = 0;
|
|
u32 cols_cfg[KBC_MAX_GPIO];
|
|
u32 rows_cfg[KBC_MAX_GPIO];
|
|
int proplen;
|
|
int ret;
|
|
|
|
if (!of_property_read_u32(np, "nvidia,debounce-delay-ms", &prop))
|
|
kbc->debounce_cnt = prop;
|
|
|
|
if (!of_property_read_u32(np, "nvidia,repeat-delay-ms", &prop))
|
|
kbc->repeat_cnt = prop;
|
|
|
|
if (of_find_property(np, "nvidia,needs-ghost-filter", NULL))
|
|
kbc->use_ghost_filter = true;
|
|
|
|
if (of_property_read_bool(np, "wakeup-source") ||
|
|
of_property_read_bool(np, "nvidia,wakeup-source")) /* legacy */
|
|
kbc->wakeup = true;
|
|
|
|
if (!of_get_property(np, "nvidia,kbc-row-pins", &proplen)) {
|
|
dev_err(kbc->dev, "property nvidia,kbc-row-pins not found\n");
|
|
return -ENOENT;
|
|
}
|
|
num_rows = proplen / sizeof(u32);
|
|
|
|
if (!of_get_property(np, "nvidia,kbc-col-pins", &proplen)) {
|
|
dev_err(kbc->dev, "property nvidia,kbc-col-pins not found\n");
|
|
return -ENOENT;
|
|
}
|
|
num_cols = proplen / sizeof(u32);
|
|
|
|
if (num_rows > kbc->hw_support->max_rows) {
|
|
dev_err(kbc->dev,
|
|
"Number of rows is more than supported by hardware\n");
|
|
return -EINVAL;
|
|
}
|
|
|
|
if (num_cols > kbc->hw_support->max_columns) {
|
|
dev_err(kbc->dev,
|
|
"Number of cols is more than supported by hardware\n");
|
|
return -EINVAL;
|
|
}
|
|
|
|
if (!of_get_property(np, "linux,keymap", &proplen)) {
|
|
dev_err(kbc->dev, "property linux,keymap not found\n");
|
|
return -ENOENT;
|
|
}
|
|
|
|
if (!num_rows || !num_cols || ((num_rows + num_cols) > KBC_MAX_GPIO)) {
|
|
dev_err(kbc->dev,
|
|
"keypad rows/columns not porperly specified\n");
|
|
return -EINVAL;
|
|
}
|
|
|
|
/* Set all pins as non-configured */
|
|
for (i = 0; i < kbc->num_rows_and_columns; i++)
|
|
kbc->pin_cfg[i].type = PIN_CFG_IGNORE;
|
|
|
|
ret = of_property_read_u32_array(np, "nvidia,kbc-row-pins",
|
|
rows_cfg, num_rows);
|
|
if (ret < 0) {
|
|
dev_err(kbc->dev, "Rows configurations are not proper\n");
|
|
return -EINVAL;
|
|
}
|
|
|
|
ret = of_property_read_u32_array(np, "nvidia,kbc-col-pins",
|
|
cols_cfg, num_cols);
|
|
if (ret < 0) {
|
|
dev_err(kbc->dev, "Cols configurations are not proper\n");
|
|
return -EINVAL;
|
|
}
|
|
|
|
for (i = 0; i < num_rows; i++) {
|
|
kbc->pin_cfg[rows_cfg[i]].type = PIN_CFG_ROW;
|
|
kbc->pin_cfg[rows_cfg[i]].num = i;
|
|
}
|
|
|
|
for (i = 0; i < num_cols; i++) {
|
|
kbc->pin_cfg[cols_cfg[i]].type = PIN_CFG_COL;
|
|
kbc->pin_cfg[cols_cfg[i]].num = i;
|
|
}
|
|
|
|
return 0;
|
|
}
|
|
|
|
static const struct tegra_kbc_hw_support tegra20_kbc_hw_support = {
|
|
.max_rows = 16,
|
|
.max_columns = 8,
|
|
};
|
|
|
|
static const struct tegra_kbc_hw_support tegra11_kbc_hw_support = {
|
|
.max_rows = 11,
|
|
.max_columns = 8,
|
|
};
|
|
|
|
static const struct of_device_id tegra_kbc_of_match[] = {
|
|
{ .compatible = "nvidia,tegra114-kbc", .data = &tegra11_kbc_hw_support},
|
|
{ .compatible = "nvidia,tegra30-kbc", .data = &tegra20_kbc_hw_support},
|
|
{ .compatible = "nvidia,tegra20-kbc", .data = &tegra20_kbc_hw_support},
|
|
{ },
|
|
};
|
|
MODULE_DEVICE_TABLE(of, tegra_kbc_of_match);
|
|
|
|
static int tegra_kbc_probe(struct platform_device *pdev)
|
|
{
|
|
struct tegra_kbc *kbc;
|
|
struct resource *res;
|
|
int err;
|
|
int num_rows = 0;
|
|
unsigned int debounce_cnt;
|
|
unsigned int scan_time_rows;
|
|
unsigned int keymap_rows;
|
|
const struct of_device_id *match;
|
|
|
|
match = of_match_device(tegra_kbc_of_match, &pdev->dev);
|
|
|
|
kbc = devm_kzalloc(&pdev->dev, sizeof(*kbc), GFP_KERNEL);
|
|
if (!kbc) {
|
|
dev_err(&pdev->dev, "failed to alloc memory for kbc\n");
|
|
return -ENOMEM;
|
|
}
|
|
|
|
kbc->dev = &pdev->dev;
|
|
kbc->hw_support = match->data;
|
|
kbc->max_keys = kbc->hw_support->max_rows *
|
|
kbc->hw_support->max_columns;
|
|
kbc->num_rows_and_columns = kbc->hw_support->max_rows +
|
|
kbc->hw_support->max_columns;
|
|
keymap_rows = kbc->max_keys;
|
|
spin_lock_init(&kbc->lock);
|
|
|
|
err = tegra_kbc_parse_dt(kbc);
|
|
if (err)
|
|
return err;
|
|
|
|
if (!tegra_kbc_check_pin_cfg(kbc, &num_rows))
|
|
return -EINVAL;
|
|
|
|
kbc->irq = platform_get_irq(pdev, 0);
|
|
if (kbc->irq < 0) {
|
|
dev_err(&pdev->dev, "failed to get keyboard IRQ\n");
|
|
return -ENXIO;
|
|
}
|
|
|
|
kbc->idev = devm_input_allocate_device(&pdev->dev);
|
|
if (!kbc->idev) {
|
|
dev_err(&pdev->dev, "failed to allocate input device\n");
|
|
return -ENOMEM;
|
|
}
|
|
|
|
setup_timer(&kbc->timer, tegra_kbc_keypress_timer, (unsigned long)kbc);
|
|
|
|
res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
|
|
kbc->mmio = devm_ioremap_resource(&pdev->dev, res);
|
|
if (IS_ERR(kbc->mmio))
|
|
return PTR_ERR(kbc->mmio);
|
|
|
|
kbc->clk = devm_clk_get(&pdev->dev, NULL);
|
|
if (IS_ERR(kbc->clk)) {
|
|
dev_err(&pdev->dev, "failed to get keyboard clock\n");
|
|
return PTR_ERR(kbc->clk);
|
|
}
|
|
|
|
kbc->rst = devm_reset_control_get(&pdev->dev, "kbc");
|
|
if (IS_ERR(kbc->rst)) {
|
|
dev_err(&pdev->dev, "failed to get keyboard reset\n");
|
|
return PTR_ERR(kbc->rst);
|
|
}
|
|
|
|
/*
|
|
* The time delay between two consecutive reads of the FIFO is
|
|
* the sum of the repeat time and the time taken for scanning
|
|
* the rows. There is an additional delay before the row scanning
|
|
* starts. The repoll delay is computed in milliseconds.
|
|
*/
|
|
debounce_cnt = min(kbc->debounce_cnt, KBC_MAX_DEBOUNCE_CNT);
|
|
scan_time_rows = (KBC_ROW_SCAN_TIME + debounce_cnt) * num_rows;
|
|
kbc->repoll_dly = KBC_ROW_SCAN_DLY + scan_time_rows + kbc->repeat_cnt;
|
|
kbc->repoll_dly = DIV_ROUND_UP(kbc->repoll_dly, KBC_CYCLE_MS);
|
|
|
|
kbc->idev->name = pdev->name;
|
|
kbc->idev->id.bustype = BUS_HOST;
|
|
kbc->idev->dev.parent = &pdev->dev;
|
|
kbc->idev->open = tegra_kbc_open;
|
|
kbc->idev->close = tegra_kbc_close;
|
|
|
|
if (kbc->keymap_data && kbc->use_fn_map)
|
|
keymap_rows *= 2;
|
|
|
|
err = matrix_keypad_build_keymap(kbc->keymap_data, NULL,
|
|
keymap_rows,
|
|
kbc->hw_support->max_columns,
|
|
kbc->keycode, kbc->idev);
|
|
if (err) {
|
|
dev_err(&pdev->dev, "failed to setup keymap\n");
|
|
return err;
|
|
}
|
|
|
|
__set_bit(EV_REP, kbc->idev->evbit);
|
|
input_set_capability(kbc->idev, EV_MSC, MSC_SCAN);
|
|
|
|
input_set_drvdata(kbc->idev, kbc);
|
|
|
|
err = devm_request_irq(&pdev->dev, kbc->irq, tegra_kbc_isr,
|
|
IRQF_TRIGGER_HIGH, pdev->name, kbc);
|
|
if (err) {
|
|
dev_err(&pdev->dev, "failed to request keyboard IRQ\n");
|
|
return err;
|
|
}
|
|
|
|
disable_irq(kbc->irq);
|
|
|
|
err = input_register_device(kbc->idev);
|
|
if (err) {
|
|
dev_err(&pdev->dev, "failed to register input device\n");
|
|
return err;
|
|
}
|
|
|
|
platform_set_drvdata(pdev, kbc);
|
|
device_init_wakeup(&pdev->dev, kbc->wakeup);
|
|
|
|
return 0;
|
|
}
|
|
|
|
#ifdef CONFIG_PM_SLEEP
|
|
static void tegra_kbc_set_keypress_interrupt(struct tegra_kbc *kbc, bool enable)
|
|
{
|
|
u32 val;
|
|
|
|
val = readl(kbc->mmio + KBC_CONTROL_0);
|
|
if (enable)
|
|
val |= KBC_CONTROL_KEYPRESS_INT_EN;
|
|
else
|
|
val &= ~KBC_CONTROL_KEYPRESS_INT_EN;
|
|
writel(val, kbc->mmio + KBC_CONTROL_0);
|
|
}
|
|
|
|
static int tegra_kbc_suspend(struct device *dev)
|
|
{
|
|
struct platform_device *pdev = to_platform_device(dev);
|
|
struct tegra_kbc *kbc = platform_get_drvdata(pdev);
|
|
|
|
mutex_lock(&kbc->idev->mutex);
|
|
if (device_may_wakeup(&pdev->dev)) {
|
|
disable_irq(kbc->irq);
|
|
del_timer_sync(&kbc->timer);
|
|
tegra_kbc_set_fifo_interrupt(kbc, false);
|
|
|
|
/* Forcefully clear the interrupt status */
|
|
writel(0x7, kbc->mmio + KBC_INT_0);
|
|
/*
|
|
* Store the previous resident time of continuous polling mode.
|
|
* Force the keyboard into interrupt mode.
|
|
*/
|
|
kbc->cp_to_wkup_dly = readl(kbc->mmio + KBC_TO_CNT_0);
|
|
writel(0, kbc->mmio + KBC_TO_CNT_0);
|
|
|
|
tegra_kbc_setup_wakekeys(kbc, true);
|
|
msleep(30);
|
|
|
|
kbc->keypress_caused_wake = false;
|
|
/* Enable keypress interrupt before going into suspend. */
|
|
tegra_kbc_set_keypress_interrupt(kbc, true);
|
|
enable_irq(kbc->irq);
|
|
enable_irq_wake(kbc->irq);
|
|
} else {
|
|
if (kbc->idev->users)
|
|
tegra_kbc_stop(kbc);
|
|
}
|
|
mutex_unlock(&kbc->idev->mutex);
|
|
|
|
return 0;
|
|
}
|
|
|
|
static int tegra_kbc_resume(struct device *dev)
|
|
{
|
|
struct platform_device *pdev = to_platform_device(dev);
|
|
struct tegra_kbc *kbc = platform_get_drvdata(pdev);
|
|
int err = 0;
|
|
|
|
mutex_lock(&kbc->idev->mutex);
|
|
if (device_may_wakeup(&pdev->dev)) {
|
|
disable_irq_wake(kbc->irq);
|
|
tegra_kbc_setup_wakekeys(kbc, false);
|
|
/* We will use fifo interrupts for key detection. */
|
|
tegra_kbc_set_keypress_interrupt(kbc, false);
|
|
|
|
/* Restore the resident time of continuous polling mode. */
|
|
writel(kbc->cp_to_wkup_dly, kbc->mmio + KBC_TO_CNT_0);
|
|
|
|
tegra_kbc_set_fifo_interrupt(kbc, true);
|
|
|
|
if (kbc->keypress_caused_wake && kbc->wakeup_key) {
|
|
/*
|
|
* We can't report events directly from the ISR
|
|
* because timekeeping is stopped when processing
|
|
* wakeup request and we get a nasty warning when
|
|
* we try to call do_gettimeofday() in evdev
|
|
* handler.
|
|
*/
|
|
input_report_key(kbc->idev, kbc->wakeup_key, 1);
|
|
input_sync(kbc->idev);
|
|
input_report_key(kbc->idev, kbc->wakeup_key, 0);
|
|
input_sync(kbc->idev);
|
|
}
|
|
} else {
|
|
if (kbc->idev->users)
|
|
err = tegra_kbc_start(kbc);
|
|
}
|
|
mutex_unlock(&kbc->idev->mutex);
|
|
|
|
return err;
|
|
}
|
|
#endif
|
|
|
|
static SIMPLE_DEV_PM_OPS(tegra_kbc_pm_ops, tegra_kbc_suspend, tegra_kbc_resume);
|
|
|
|
static struct platform_driver tegra_kbc_driver = {
|
|
.probe = tegra_kbc_probe,
|
|
.driver = {
|
|
.name = "tegra-kbc",
|
|
.pm = &tegra_kbc_pm_ops,
|
|
.of_match_table = tegra_kbc_of_match,
|
|
},
|
|
};
|
|
module_platform_driver(tegra_kbc_driver);
|
|
|
|
MODULE_LICENSE("GPL");
|
|
MODULE_AUTHOR("Rakesh Iyer <riyer@nvidia.com>");
|
|
MODULE_DESCRIPTION("Tegra matrix keyboard controller driver");
|
|
MODULE_ALIAS("platform:tegra-kbc");
|