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9488e1e5b3
The device tree probing for R-Car M2N (r8a7793) is added. Signed-off-by: Hisashi Nakamura <hisashi.nakamura.ak@renesas.com> Signed-off-by: Yoshihiro Kaneko <ykaneko0929@gmail.com> Signed-off-by: David S. Miller <davem@davemloft.net>
58 lines
2.3 KiB
Plaintext
58 lines
2.3 KiB
Plaintext
* Renesas Electronics SH EtherMAC
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This file provides information on what the device node for the SH EtherMAC
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interface contains.
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Required properties:
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- compatible: "renesas,gether-r8a7740" if the device is a part of R8A7740 SoC.
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"renesas,ether-r8a7778" if the device is a part of R8A7778 SoC.
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"renesas,ether-r8a7779" if the device is a part of R8A7779 SoC.
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"renesas,ether-r8a7790" if the device is a part of R8A7790 SoC.
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"renesas,ether-r8a7791" if the device is a part of R8A7791 SoC.
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"renesas,ether-r8a7793" if the device is a part of R8A7793 SoC.
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"renesas,ether-r8a7794" if the device is a part of R8A7794 SoC.
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"renesas,ether-r7s72100" if the device is a part of R7S72100 SoC.
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- reg: offset and length of (1) the E-DMAC/feLic register block (required),
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(2) the TSU register block (optional).
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- interrupts: interrupt specifier for the sole interrupt.
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- phy-mode: see ethernet.txt file in the same directory.
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- phy-handle: see ethernet.txt file in the same directory.
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- #address-cells: number of address cells for the MDIO bus, must be equal to 1.
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- #size-cells: number of size cells on the MDIO bus, must be equal to 0.
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- clocks: clock phandle and specifier pair.
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- pinctrl-0: phandle, referring to a default pin configuration node.
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Optional properties:
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- interrupt-parent: the phandle for the interrupt controller that services
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interrupts for this device.
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- pinctrl-names: pin configuration state name ("default").
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- renesas,no-ether-link: boolean, specify when a board does not provide a proper
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Ether LINK signal.
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- renesas,ether-link-active-low: boolean, specify when the Ether LINK signal is
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active-low instead of normal active-high.
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Example (Lager board):
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ethernet@ee700000 {
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compatible = "renesas,ether-r8a7790";
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reg = <0 0xee700000 0 0x400>;
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interrupt-parent = <&gic>;
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interrupts = <0 162 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&mstp8_clks R8A7790_CLK_ETHER>;
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phy-mode = "rmii";
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phy-handle = <&phy1>;
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pinctrl-0 = <ðer_pins>;
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pinctrl-names = "default";
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renesas,ether-link-active-low;
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#address-cells = <1>;
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#size-cells = <0>;
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phy1: ethernet-phy@1 {
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reg = <1>;
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interrupt-parent = <&irqc0>;
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interrupts = <0 IRQ_TYPE_LEVEL_LOW>;
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pinctrl-0 = <&phy1_pins>;
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pinctrl-names = "default";
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};
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};
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