mirror of
https://github.com/AuxXxilium/linux_dsm_epyc7002.git
synced 2024-12-06 00:56:39 +07:00
76b1a87b21
Instead of the PCI code needing to have code to determine the cacheline size of each processor, use the data the cpu identification code should have already determined during early boot. (The vendor checks are also incomplete, and don't take into account modern CPUs) I've been carrying a variant of this code in Fedora for a while, that prints debug information. There are a number of cases where we are currently setting the PCI cacheline size to 32 bytes, when the CPU cacheline size is 64 bytes. With this patch, we set them both the same. Signed-off-by: Dave Jones <davej@redhat.com> Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org>
674 lines
15 KiB
C
674 lines
15 KiB
C
/*
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* Low-Level PCI Support for PC
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*
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* (c) 1999--2000 Martin Mares <mj@ucw.cz>
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*/
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#include <linux/sched.h>
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#include <linux/pci.h>
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#include <linux/ioport.h>
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#include <linux/init.h>
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#include <linux/dmi.h>
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#include <asm/acpi.h>
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#include <asm/segment.h>
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#include <asm/io.h>
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#include <asm/smp.h>
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#include <asm/pci_x86.h>
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unsigned int pci_probe = PCI_PROBE_BIOS | PCI_PROBE_CONF1 | PCI_PROBE_CONF2 |
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PCI_PROBE_MMCONF;
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unsigned int pci_early_dump_regs;
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static int pci_bf_sort;
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int pci_routeirq;
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int noioapicquirk;
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#ifdef CONFIG_X86_REROUTE_FOR_BROKEN_BOOT_IRQS
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int noioapicreroute = 0;
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#else
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int noioapicreroute = 1;
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#endif
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int pcibios_last_bus = -1;
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unsigned long pirq_table_addr;
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struct pci_bus *pci_root_bus;
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struct pci_raw_ops *raw_pci_ops;
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struct pci_raw_ops *raw_pci_ext_ops;
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int raw_pci_read(unsigned int domain, unsigned int bus, unsigned int devfn,
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int reg, int len, u32 *val)
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{
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if (domain == 0 && reg < 256 && raw_pci_ops)
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return raw_pci_ops->read(domain, bus, devfn, reg, len, val);
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if (raw_pci_ext_ops)
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return raw_pci_ext_ops->read(domain, bus, devfn, reg, len, val);
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return -EINVAL;
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}
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int raw_pci_write(unsigned int domain, unsigned int bus, unsigned int devfn,
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int reg, int len, u32 val)
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{
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if (domain == 0 && reg < 256 && raw_pci_ops)
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return raw_pci_ops->write(domain, bus, devfn, reg, len, val);
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if (raw_pci_ext_ops)
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return raw_pci_ext_ops->write(domain, bus, devfn, reg, len, val);
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return -EINVAL;
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}
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static int pci_read(struct pci_bus *bus, unsigned int devfn, int where, int size, u32 *value)
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{
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return raw_pci_read(pci_domain_nr(bus), bus->number,
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devfn, where, size, value);
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}
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static int pci_write(struct pci_bus *bus, unsigned int devfn, int where, int size, u32 value)
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{
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return raw_pci_write(pci_domain_nr(bus), bus->number,
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devfn, where, size, value);
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}
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struct pci_ops pci_root_ops = {
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.read = pci_read,
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.write = pci_write,
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};
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/*
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* legacy, numa, and acpi all want to call pcibios_scan_root
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* from their initcalls. This flag prevents that.
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*/
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int pcibios_scanned;
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/*
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* This interrupt-safe spinlock protects all accesses to PCI
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* configuration space.
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*/
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DEFINE_SPINLOCK(pci_config_lock);
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static int __devinit can_skip_ioresource_align(const struct dmi_system_id *d)
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{
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pci_probe |= PCI_CAN_SKIP_ISA_ALIGN;
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printk(KERN_INFO "PCI: %s detected, can skip ISA alignment\n", d->ident);
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return 0;
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}
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static const struct dmi_system_id can_skip_pciprobe_dmi_table[] __devinitconst = {
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/*
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* Systems where PCI IO resource ISA alignment can be skipped
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* when the ISA enable bit in the bridge control is not set
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*/
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{
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.callback = can_skip_ioresource_align,
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.ident = "IBM System x3800",
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.matches = {
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DMI_MATCH(DMI_SYS_VENDOR, "IBM"),
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DMI_MATCH(DMI_PRODUCT_NAME, "x3800"),
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},
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},
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{
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.callback = can_skip_ioresource_align,
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.ident = "IBM System x3850",
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.matches = {
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DMI_MATCH(DMI_SYS_VENDOR, "IBM"),
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DMI_MATCH(DMI_PRODUCT_NAME, "x3850"),
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},
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},
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{
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.callback = can_skip_ioresource_align,
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.ident = "IBM System x3950",
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.matches = {
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DMI_MATCH(DMI_SYS_VENDOR, "IBM"),
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DMI_MATCH(DMI_PRODUCT_NAME, "x3950"),
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},
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},
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{}
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};
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void __init dmi_check_skip_isa_align(void)
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{
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dmi_check_system(can_skip_pciprobe_dmi_table);
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}
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static void __devinit pcibios_fixup_device_resources(struct pci_dev *dev)
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{
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struct resource *rom_r = &dev->resource[PCI_ROM_RESOURCE];
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if (pci_probe & PCI_NOASSIGN_ROMS) {
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if (rom_r->parent)
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return;
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if (rom_r->start) {
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/* we deal with BIOS assigned ROM later */
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return;
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}
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rom_r->start = rom_r->end = rom_r->flags = 0;
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}
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}
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/*
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* Called after each bus is probed, but before its children
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* are examined.
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*/
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void __devinit pcibios_fixup_bus(struct pci_bus *b)
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{
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struct pci_dev *dev;
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/* root bus? */
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if (!b->parent)
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x86_pci_root_bus_res_quirks(b);
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pci_read_bridge_bases(b);
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list_for_each_entry(dev, &b->devices, bus_list)
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pcibios_fixup_device_resources(dev);
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}
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/*
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* Only use DMI information to set this if nothing was passed
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* on the kernel command line (which was parsed earlier).
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*/
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static int __devinit set_bf_sort(const struct dmi_system_id *d)
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{
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if (pci_bf_sort == pci_bf_sort_default) {
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pci_bf_sort = pci_dmi_bf;
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printk(KERN_INFO "PCI: %s detected, enabling pci=bfsort.\n", d->ident);
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}
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return 0;
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}
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/*
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* Enable renumbering of PCI bus# ranges to reach all PCI busses (Cardbus)
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*/
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#ifdef __i386__
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static int __devinit assign_all_busses(const struct dmi_system_id *d)
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{
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pci_probe |= PCI_ASSIGN_ALL_BUSSES;
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printk(KERN_INFO "%s detected: enabling PCI bus# renumbering"
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" (pci=assign-busses)\n", d->ident);
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return 0;
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}
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#endif
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static const struct dmi_system_id __devinitconst pciprobe_dmi_table[] = {
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#ifdef __i386__
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/*
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* Laptops which need pci=assign-busses to see Cardbus cards
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*/
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{
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.callback = assign_all_busses,
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.ident = "Samsung X20 Laptop",
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.matches = {
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DMI_MATCH(DMI_SYS_VENDOR, "Samsung Electronics"),
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DMI_MATCH(DMI_PRODUCT_NAME, "SX20S"),
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},
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},
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#endif /* __i386__ */
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{
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.callback = set_bf_sort,
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.ident = "Dell PowerEdge 1950",
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.matches = {
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DMI_MATCH(DMI_SYS_VENDOR, "Dell"),
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DMI_MATCH(DMI_PRODUCT_NAME, "PowerEdge 1950"),
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},
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},
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{
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.callback = set_bf_sort,
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.ident = "Dell PowerEdge 1955",
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.matches = {
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DMI_MATCH(DMI_SYS_VENDOR, "Dell"),
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DMI_MATCH(DMI_PRODUCT_NAME, "PowerEdge 1955"),
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},
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},
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{
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.callback = set_bf_sort,
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.ident = "Dell PowerEdge 2900",
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.matches = {
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DMI_MATCH(DMI_SYS_VENDOR, "Dell"),
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DMI_MATCH(DMI_PRODUCT_NAME, "PowerEdge 2900"),
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},
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},
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{
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.callback = set_bf_sort,
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.ident = "Dell PowerEdge 2950",
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.matches = {
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DMI_MATCH(DMI_SYS_VENDOR, "Dell"),
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DMI_MATCH(DMI_PRODUCT_NAME, "PowerEdge 2950"),
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},
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},
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{
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.callback = set_bf_sort,
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.ident = "Dell PowerEdge R900",
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.matches = {
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DMI_MATCH(DMI_SYS_VENDOR, "Dell"),
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DMI_MATCH(DMI_PRODUCT_NAME, "PowerEdge R900"),
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},
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},
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{
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.callback = set_bf_sort,
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.ident = "HP ProLiant BL20p G3",
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.matches = {
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DMI_MATCH(DMI_SYS_VENDOR, "HP"),
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DMI_MATCH(DMI_PRODUCT_NAME, "ProLiant BL20p G3"),
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},
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},
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{
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.callback = set_bf_sort,
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.ident = "HP ProLiant BL20p G4",
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.matches = {
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DMI_MATCH(DMI_SYS_VENDOR, "HP"),
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DMI_MATCH(DMI_PRODUCT_NAME, "ProLiant BL20p G4"),
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},
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},
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{
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.callback = set_bf_sort,
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.ident = "HP ProLiant BL30p G1",
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.matches = {
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DMI_MATCH(DMI_SYS_VENDOR, "HP"),
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DMI_MATCH(DMI_PRODUCT_NAME, "ProLiant BL30p G1"),
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},
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},
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{
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.callback = set_bf_sort,
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.ident = "HP ProLiant BL25p G1",
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.matches = {
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DMI_MATCH(DMI_SYS_VENDOR, "HP"),
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DMI_MATCH(DMI_PRODUCT_NAME, "ProLiant BL25p G1"),
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},
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},
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{
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.callback = set_bf_sort,
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.ident = "HP ProLiant BL35p G1",
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.matches = {
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DMI_MATCH(DMI_SYS_VENDOR, "HP"),
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DMI_MATCH(DMI_PRODUCT_NAME, "ProLiant BL35p G1"),
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},
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},
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{
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.callback = set_bf_sort,
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.ident = "HP ProLiant BL45p G1",
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.matches = {
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DMI_MATCH(DMI_SYS_VENDOR, "HP"),
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DMI_MATCH(DMI_PRODUCT_NAME, "ProLiant BL45p G1"),
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},
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},
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{
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.callback = set_bf_sort,
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.ident = "HP ProLiant BL45p G2",
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.matches = {
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DMI_MATCH(DMI_SYS_VENDOR, "HP"),
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DMI_MATCH(DMI_PRODUCT_NAME, "ProLiant BL45p G2"),
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},
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},
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{
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.callback = set_bf_sort,
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.ident = "HP ProLiant BL460c G1",
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.matches = {
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DMI_MATCH(DMI_SYS_VENDOR, "HP"),
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DMI_MATCH(DMI_PRODUCT_NAME, "ProLiant BL460c G1"),
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},
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},
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{
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.callback = set_bf_sort,
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.ident = "HP ProLiant BL465c G1",
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.matches = {
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DMI_MATCH(DMI_SYS_VENDOR, "HP"),
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DMI_MATCH(DMI_PRODUCT_NAME, "ProLiant BL465c G1"),
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},
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},
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{
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.callback = set_bf_sort,
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.ident = "HP ProLiant BL480c G1",
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.matches = {
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DMI_MATCH(DMI_SYS_VENDOR, "HP"),
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DMI_MATCH(DMI_PRODUCT_NAME, "ProLiant BL480c G1"),
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},
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},
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{
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.callback = set_bf_sort,
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.ident = "HP ProLiant BL685c G1",
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.matches = {
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DMI_MATCH(DMI_SYS_VENDOR, "HP"),
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DMI_MATCH(DMI_PRODUCT_NAME, "ProLiant BL685c G1"),
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},
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},
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{
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.callback = set_bf_sort,
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.ident = "HP ProLiant DL360",
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.matches = {
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DMI_MATCH(DMI_SYS_VENDOR, "HP"),
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DMI_MATCH(DMI_PRODUCT_NAME, "ProLiant DL360"),
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},
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},
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{
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.callback = set_bf_sort,
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.ident = "HP ProLiant DL380",
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.matches = {
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DMI_MATCH(DMI_SYS_VENDOR, "HP"),
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DMI_MATCH(DMI_PRODUCT_NAME, "ProLiant DL380"),
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},
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},
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#ifdef __i386__
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{
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.callback = assign_all_busses,
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.ident = "Compaq EVO N800c",
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.matches = {
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DMI_MATCH(DMI_SYS_VENDOR, "Compaq"),
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DMI_MATCH(DMI_PRODUCT_NAME, "EVO N800c"),
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},
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},
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#endif
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{
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.callback = set_bf_sort,
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.ident = "HP ProLiant DL385 G2",
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.matches = {
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DMI_MATCH(DMI_SYS_VENDOR, "HP"),
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DMI_MATCH(DMI_PRODUCT_NAME, "ProLiant DL385 G2"),
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},
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},
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{
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.callback = set_bf_sort,
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.ident = "HP ProLiant DL585 G2",
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.matches = {
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DMI_MATCH(DMI_SYS_VENDOR, "HP"),
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DMI_MATCH(DMI_PRODUCT_NAME, "ProLiant DL585 G2"),
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},
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},
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{}
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};
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void __init dmi_check_pciprobe(void)
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{
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dmi_check_system(pciprobe_dmi_table);
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}
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struct pci_bus * __devinit pcibios_scan_root(int busnum)
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{
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struct pci_bus *bus = NULL;
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struct pci_sysdata *sd;
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while ((bus = pci_find_next_bus(bus)) != NULL) {
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if (bus->number == busnum) {
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/* Already scanned */
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return bus;
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}
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}
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/* Allocate per-root-bus (not per bus) arch-specific data.
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* TODO: leak; this memory is never freed.
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* It's arguable whether it's worth the trouble to care.
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*/
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sd = kzalloc(sizeof(*sd), GFP_KERNEL);
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if (!sd) {
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printk(KERN_ERR "PCI: OOM, not probing PCI bus %02x\n", busnum);
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return NULL;
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}
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sd->node = get_mp_bus_to_node(busnum);
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printk(KERN_DEBUG "PCI: Probing PCI hardware (bus %02x)\n", busnum);
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bus = pci_scan_bus_parented(NULL, busnum, &pci_root_ops, sd);
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if (!bus)
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kfree(sd);
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return bus;
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}
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int __init pcibios_init(void)
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{
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struct cpuinfo_x86 *c = &boot_cpu_data;
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if (!raw_pci_ops) {
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printk(KERN_WARNING "PCI: System does not support PCI\n");
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return 0;
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}
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/*
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* Set PCI cacheline size to that of the CPU if the CPU has reported it.
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* (For older CPUs that don't support cpuid, we se it to 32 bytes
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* It's also good for 386/486s (which actually have 16)
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* as quite a few PCI devices do not support smaller values.
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*/
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if (c->x86_clflush_size > 0) {
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pci_dfl_cache_line_size = c->x86_clflush_size >> 2;
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printk(KERN_DEBUG "PCI: pci_cache_line_size set to %d bytes\n",
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pci_dfl_cache_line_size << 2);
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} else {
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pci_dfl_cache_line_size = 32 >> 2;
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printk(KERN_DEBUG "PCI: Unknown cacheline size. Setting to 32 bytes\n");
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}
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pcibios_resource_survey();
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if (pci_bf_sort >= pci_force_bf)
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pci_sort_breadthfirst();
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return 0;
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}
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char * __devinit pcibios_setup(char *str)
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{
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if (!strcmp(str, "off")) {
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pci_probe = 0;
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return NULL;
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} else if (!strcmp(str, "bfsort")) {
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pci_bf_sort = pci_force_bf;
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return NULL;
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} else if (!strcmp(str, "nobfsort")) {
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pci_bf_sort = pci_force_nobf;
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return NULL;
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}
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#ifdef CONFIG_PCI_BIOS
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else if (!strcmp(str, "bios")) {
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pci_probe = PCI_PROBE_BIOS;
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return NULL;
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} else if (!strcmp(str, "nobios")) {
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pci_probe &= ~PCI_PROBE_BIOS;
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return NULL;
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} else if (!strcmp(str, "biosirq")) {
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pci_probe |= PCI_BIOS_IRQ_SCAN;
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return NULL;
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} else if (!strncmp(str, "pirqaddr=", 9)) {
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pirq_table_addr = simple_strtoul(str+9, NULL, 0);
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return NULL;
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}
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#endif
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#ifdef CONFIG_PCI_DIRECT
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else if (!strcmp(str, "conf1")) {
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pci_probe = PCI_PROBE_CONF1 | PCI_NO_CHECKS;
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return NULL;
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}
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else if (!strcmp(str, "conf2")) {
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pci_probe = PCI_PROBE_CONF2 | PCI_NO_CHECKS;
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return NULL;
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}
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#endif
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#ifdef CONFIG_PCI_MMCONFIG
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else if (!strcmp(str, "nommconf")) {
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pci_probe &= ~PCI_PROBE_MMCONF;
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return NULL;
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}
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else if (!strcmp(str, "check_enable_amd_mmconf")) {
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pci_probe |= PCI_CHECK_ENABLE_AMD_MMCONF;
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return NULL;
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}
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#endif
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else if (!strcmp(str, "noacpi")) {
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acpi_noirq_set();
|
|
return NULL;
|
|
}
|
|
else if (!strcmp(str, "noearly")) {
|
|
pci_probe |= PCI_PROBE_NOEARLY;
|
|
return NULL;
|
|
}
|
|
#ifndef CONFIG_X86_VISWS
|
|
else if (!strcmp(str, "usepirqmask")) {
|
|
pci_probe |= PCI_USE_PIRQ_MASK;
|
|
return NULL;
|
|
} else if (!strncmp(str, "irqmask=", 8)) {
|
|
pcibios_irq_mask = simple_strtol(str+8, NULL, 0);
|
|
return NULL;
|
|
} else if (!strncmp(str, "lastbus=", 8)) {
|
|
pcibios_last_bus = simple_strtol(str+8, NULL, 0);
|
|
return NULL;
|
|
}
|
|
#endif
|
|
else if (!strcmp(str, "rom")) {
|
|
pci_probe |= PCI_ASSIGN_ROMS;
|
|
return NULL;
|
|
} else if (!strcmp(str, "norom")) {
|
|
pci_probe |= PCI_NOASSIGN_ROMS;
|
|
return NULL;
|
|
} else if (!strcmp(str, "assign-busses")) {
|
|
pci_probe |= PCI_ASSIGN_ALL_BUSSES;
|
|
return NULL;
|
|
} else if (!strcmp(str, "use_crs")) {
|
|
pci_probe |= PCI_USE__CRS;
|
|
return NULL;
|
|
} else if (!strcmp(str, "earlydump")) {
|
|
pci_early_dump_regs = 1;
|
|
return NULL;
|
|
} else if (!strcmp(str, "routeirq")) {
|
|
pci_routeirq = 1;
|
|
return NULL;
|
|
} else if (!strcmp(str, "skip_isa_align")) {
|
|
pci_probe |= PCI_CAN_SKIP_ISA_ALIGN;
|
|
return NULL;
|
|
} else if (!strcmp(str, "noioapicquirk")) {
|
|
noioapicquirk = 1;
|
|
return NULL;
|
|
} else if (!strcmp(str, "ioapicreroute")) {
|
|
if (noioapicreroute != -1)
|
|
noioapicreroute = 0;
|
|
return NULL;
|
|
} else if (!strcmp(str, "noioapicreroute")) {
|
|
if (noioapicreroute != -1)
|
|
noioapicreroute = 1;
|
|
return NULL;
|
|
}
|
|
return str;
|
|
}
|
|
|
|
unsigned int pcibios_assign_all_busses(void)
|
|
{
|
|
return (pci_probe & PCI_ASSIGN_ALL_BUSSES) ? 1 : 0;
|
|
}
|
|
|
|
int pcibios_enable_device(struct pci_dev *dev, int mask)
|
|
{
|
|
int err;
|
|
|
|
if ((err = pci_enable_resources(dev, mask)) < 0)
|
|
return err;
|
|
|
|
if (!pci_dev_msi_enabled(dev))
|
|
return pcibios_enable_irq(dev);
|
|
return 0;
|
|
}
|
|
|
|
void pcibios_disable_device (struct pci_dev *dev)
|
|
{
|
|
if (!pci_dev_msi_enabled(dev) && pcibios_disable_irq)
|
|
pcibios_disable_irq(dev);
|
|
}
|
|
|
|
int pci_ext_cfg_avail(struct pci_dev *dev)
|
|
{
|
|
if (raw_pci_ext_ops)
|
|
return 1;
|
|
else
|
|
return 0;
|
|
}
|
|
|
|
struct pci_bus * __devinit pci_scan_bus_on_node(int busno, struct pci_ops *ops, int node)
|
|
{
|
|
struct pci_bus *bus = NULL;
|
|
struct pci_sysdata *sd;
|
|
|
|
/*
|
|
* Allocate per-root-bus (not per bus) arch-specific data.
|
|
* TODO: leak; this memory is never freed.
|
|
* It's arguable whether it's worth the trouble to care.
|
|
*/
|
|
sd = kzalloc(sizeof(*sd), GFP_KERNEL);
|
|
if (!sd) {
|
|
printk(KERN_ERR "PCI: OOM, skipping PCI bus %02x\n", busno);
|
|
return NULL;
|
|
}
|
|
sd->node = node;
|
|
bus = pci_scan_bus(busno, ops, sd);
|
|
if (!bus)
|
|
kfree(sd);
|
|
|
|
return bus;
|
|
}
|
|
|
|
struct pci_bus * __devinit pci_scan_bus_with_sysdata(int busno)
|
|
{
|
|
return pci_scan_bus_on_node(busno, &pci_root_ops, -1);
|
|
}
|
|
|
|
/*
|
|
* NUMA info for PCI busses
|
|
*
|
|
* Early arch code is responsible for filling in reasonable values here.
|
|
* A node id of "-1" means "use current node". In other words, if a bus
|
|
* has a -1 node id, it's not tightly coupled to any particular chunk
|
|
* of memory (as is the case on some Nehalem systems).
|
|
*/
|
|
#ifdef CONFIG_NUMA
|
|
|
|
#define BUS_NR 256
|
|
|
|
#ifdef CONFIG_X86_64
|
|
|
|
static int mp_bus_to_node[BUS_NR] = {
|
|
[0 ... BUS_NR - 1] = -1
|
|
};
|
|
|
|
void set_mp_bus_to_node(int busnum, int node)
|
|
{
|
|
if (busnum >= 0 && busnum < BUS_NR)
|
|
mp_bus_to_node[busnum] = node;
|
|
}
|
|
|
|
int get_mp_bus_to_node(int busnum)
|
|
{
|
|
int node = -1;
|
|
|
|
if (busnum < 0 || busnum > (BUS_NR - 1))
|
|
return node;
|
|
|
|
node = mp_bus_to_node[busnum];
|
|
|
|
/*
|
|
* let numa_node_id to decide it later in dma_alloc_pages
|
|
* if there is no ram on that node
|
|
*/
|
|
if (node != -1 && !node_online(node))
|
|
node = -1;
|
|
|
|
return node;
|
|
}
|
|
|
|
#else /* CONFIG_X86_32 */
|
|
|
|
static int mp_bus_to_node[BUS_NR] = {
|
|
[0 ... BUS_NR - 1] = -1
|
|
};
|
|
|
|
void set_mp_bus_to_node(int busnum, int node)
|
|
{
|
|
if (busnum >= 0 && busnum < BUS_NR)
|
|
mp_bus_to_node[busnum] = (unsigned char) node;
|
|
}
|
|
|
|
int get_mp_bus_to_node(int busnum)
|
|
{
|
|
int node;
|
|
|
|
if (busnum < 0 || busnum > (BUS_NR - 1))
|
|
return 0;
|
|
node = mp_bus_to_node[busnum];
|
|
return node;
|
|
}
|
|
|
|
#endif /* CONFIG_X86_32 */
|
|
|
|
#endif /* CONFIG_NUMA */
|