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https://github.com/AuxXxilium/linux_dsm_epyc7002.git
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974b6289e8
[ Upstream commit a44092e326d403c7878018ba532369f84d31dbfa ] IOMMU Extended Feature Register (EFR) is used to communicate the supported features for each IOMMU to the IOMMU driver. This is normally read from the PCI MMIO register offset 0x30, and used by the iommu_feature() helper function. However, there are certain scenarios where the information is needed prior to PCI initialization, and the iommu_feature() function is used prematurely w/o warning. This has caused incorrect initialization of IOMMU. This is the case for the commit6d39bdee23("iommu/amd: Enforce 4k mapping for certain IOMMU data structures") Since, the EFR is also available in the IVHD header, and is available to the driver prior to PCI initialization. Therefore, default to using the IVHD EFR instead. Fixes:6d39bdee23("iommu/amd: Enforce 4k mapping for certain IOMMU data structures") Signed-off-by: Suravee Suthikulpanit <suravee.suthikulpanit@amd.com> Tested-by: Brijesh Singh <brijesh.singh@amd.com> Reviewed-by: Robert Richter <rrichter@amd.com> Link: https://lore.kernel.org/r/20210120135002.2682-1-suravee.suthikulpanit@amd.com Signed-off-by: Joerg Roedel <jroedel@suse.de> Signed-off-by: Sasha Levin <sashal@kernel.org>
115 lines
3.6 KiB
C
115 lines
3.6 KiB
C
/* SPDX-License-Identifier: GPL-2.0-only */
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/*
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* Copyright (C) 2009-2010 Advanced Micro Devices, Inc.
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* Author: Joerg Roedel <jroedel@suse.de>
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*/
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#ifndef AMD_IOMMU_H
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#define AMD_IOMMU_H
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#include <linux/iommu.h>
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#include "amd_iommu_types.h"
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extern int amd_iommu_get_num_iommus(void);
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extern int amd_iommu_init_dma_ops(void);
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extern int amd_iommu_init_passthrough(void);
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extern irqreturn_t amd_iommu_int_thread(int irq, void *data);
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extern irqreturn_t amd_iommu_int_handler(int irq, void *data);
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extern void amd_iommu_apply_erratum_63(u16 devid);
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extern void amd_iommu_reset_cmd_buffer(struct amd_iommu *iommu);
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extern int amd_iommu_init_devices(void);
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extern void amd_iommu_uninit_devices(void);
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extern void amd_iommu_init_notifier(void);
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extern int amd_iommu_init_api(void);
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#ifdef CONFIG_AMD_IOMMU_DEBUGFS
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void amd_iommu_debugfs_setup(struct amd_iommu *iommu);
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#else
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static inline void amd_iommu_debugfs_setup(struct amd_iommu *iommu) {}
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#endif
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/* Needed for interrupt remapping */
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extern int amd_iommu_prepare(void);
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extern int amd_iommu_enable(void);
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extern void amd_iommu_disable(void);
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extern int amd_iommu_reenable(int);
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extern int amd_iommu_enable_faulting(void);
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extern int amd_iommu_guest_ir;
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/* IOMMUv2 specific functions */
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struct iommu_domain;
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extern bool amd_iommu_v2_supported(void);
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extern struct amd_iommu *get_amd_iommu(unsigned int idx);
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extern u8 amd_iommu_pc_get_max_banks(unsigned int idx);
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extern bool amd_iommu_pc_supported(void);
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extern u8 amd_iommu_pc_get_max_counters(unsigned int idx);
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extern int amd_iommu_pc_get_reg(struct amd_iommu *iommu, u8 bank, u8 cntr,
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u8 fxn, u64 *value);
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extern int amd_iommu_pc_set_reg(struct amd_iommu *iommu, u8 bank, u8 cntr,
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u8 fxn, u64 *value);
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extern int amd_iommu_register_ppr_notifier(struct notifier_block *nb);
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extern int amd_iommu_unregister_ppr_notifier(struct notifier_block *nb);
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extern void amd_iommu_domain_direct_map(struct iommu_domain *dom);
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extern int amd_iommu_domain_enable_v2(struct iommu_domain *dom, int pasids);
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extern int amd_iommu_flush_page(struct iommu_domain *dom, u32 pasid,
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u64 address);
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extern int amd_iommu_flush_tlb(struct iommu_domain *dom, u32 pasid);
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extern int amd_iommu_domain_set_gcr3(struct iommu_domain *dom, u32 pasid,
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unsigned long cr3);
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extern int amd_iommu_domain_clear_gcr3(struct iommu_domain *dom, u32 pasid);
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extern struct iommu_domain *amd_iommu_get_v2_domain(struct pci_dev *pdev);
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#ifdef CONFIG_IRQ_REMAP
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extern int amd_iommu_create_irq_domain(struct amd_iommu *iommu);
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#else
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static inline int amd_iommu_create_irq_domain(struct amd_iommu *iommu)
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{
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return 0;
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}
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#endif
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#define PPR_SUCCESS 0x0
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#define PPR_INVALID 0x1
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#define PPR_FAILURE 0xf
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extern int amd_iommu_complete_ppr(struct pci_dev *pdev, u32 pasid,
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int status, int tag);
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static inline bool is_rd890_iommu(struct pci_dev *pdev)
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{
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return (pdev->vendor == PCI_VENDOR_ID_ATI) &&
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(pdev->device == PCI_DEVICE_ID_RD890_IOMMU);
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}
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static inline bool iommu_feature(struct amd_iommu *iommu, u64 mask)
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{
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return !!(iommu->features & mask);
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}
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static inline u64 iommu_virt_to_phys(void *vaddr)
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{
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return (u64)__sme_set(virt_to_phys(vaddr));
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}
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static inline void *iommu_phys_to_virt(unsigned long paddr)
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{
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return phys_to_virt(__sme_clr(paddr));
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}
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extern bool translation_pre_enabled(struct amd_iommu *iommu);
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extern bool amd_iommu_is_attach_deferred(struct iommu_domain *domain,
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struct device *dev);
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extern int __init add_special_device(u8 type, u8 id, u16 *devid,
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bool cmd_line);
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#ifdef CONFIG_DMI
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void amd_iommu_apply_ivrs_quirks(void);
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#else
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static inline void amd_iommu_apply_ivrs_quirks(void) { }
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#endif
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#endif
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