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3b4b82399c
Commit 7c151d3d5d ("MIPS: Make use of the ERETNC instruction on MIPS
R6") began clearing LLBit during context switches, but did so on all
systems where it is writable for unclear reasons & did so from a macro
with "software_ll_bit" in its name, which is intended to operate on the
ll_bit variable used by ll/sc emulation for old CPUs.
We do now need to clear LLBit on MIPSr6 systems where we'll use eretnc
to return to userland, but we don't need to do so on MIPSr5 systems with
a writable LLBit.
Move the clear to its own appropriately named macro, do it only for
MIPSr6 systems & comment about why.
Signed-off-by: Paul Burton <paul.burton@imgtec.com>
Cc: linux-mips@linux-mips.org
Patchwork: https://patchwork.linux-mips.org/patch/14409/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
137 lines
4.2 KiB
C
137 lines
4.2 KiB
C
/*
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* This file is subject to the terms and conditions of the GNU General Public
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* License. See the file "COPYING" in the main directory of this archive
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* for more details.
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*
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* Copyright (C) 1994, 95, 96, 97, 98, 99, 2003, 06 by Ralf Baechle
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* Copyright (C) 1996 by Paul M. Antoine
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* Copyright (C) 1999 Silicon Graphics
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* Kevin D. Kissell, kevink@mips.org and Carsten Langgaard, carstenl@mips.com
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* Copyright (C) 2000 MIPS Technologies, Inc.
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*/
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#ifndef _ASM_SWITCH_TO_H
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#define _ASM_SWITCH_TO_H
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#include <asm/cpu-features.h>
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#include <asm/watch.h>
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#include <asm/dsp.h>
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#include <asm/cop2.h>
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#include <asm/fpu.h>
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struct task_struct;
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/**
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* resume - resume execution of a task
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* @prev: The task previously executed.
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* @next: The task to begin executing.
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* @next_ti: task_thread_info(next).
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*
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* This function is used whilst scheduling to save the context of prev & load
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* the context of next. Returns prev.
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*/
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extern asmlinkage struct task_struct *resume(struct task_struct *prev,
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struct task_struct *next, struct thread_info *next_ti);
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extern unsigned int ll_bit;
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extern struct task_struct *ll_task;
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#ifdef CONFIG_MIPS_MT_FPAFF
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/*
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* Handle the scheduler resume end of FPU affinity management. We do this
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* inline to try to keep the overhead down. If we have been forced to run on
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* a "CPU" with an FPU because of a previous high level of FP computation,
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* but did not actually use the FPU during the most recent time-slice (CU1
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* isn't set), we undo the restriction on cpus_allowed.
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*
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* We're not calling set_cpus_allowed() here, because we have no need to
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* force prompt migration - we're already switching the current CPU to a
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* different thread.
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*/
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#define __mips_mt_fpaff_switch_to(prev) \
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do { \
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struct thread_info *__prev_ti = task_thread_info(prev); \
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\
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if (cpu_has_fpu && \
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test_ti_thread_flag(__prev_ti, TIF_FPUBOUND) && \
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(!(KSTK_STATUS(prev) & ST0_CU1))) { \
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clear_ti_thread_flag(__prev_ti, TIF_FPUBOUND); \
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prev->cpus_allowed = prev->thread.user_cpus_allowed; \
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} \
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next->thread.emulated_fp = 0; \
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} while(0)
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#else
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#define __mips_mt_fpaff_switch_to(prev) do { (void) (prev); } while (0)
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#endif
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/*
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* Clear LLBit during context switches on MIPSr6 such that eretnc can be used
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* unconditionally when returning to userland in entry.S.
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*/
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#define __clear_r6_hw_ll_bit() do { \
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if (cpu_has_mips_r6) \
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write_c0_lladdr(0); \
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} while (0)
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#define __clear_software_ll_bit() do { \
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if (!__builtin_constant_p(cpu_has_llsc) || !cpu_has_llsc) \
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ll_bit = 0; \
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} while (0)
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/*
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* Check FCSR for any unmasked exceptions pending set with `ptrace',
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* clear them and send a signal.
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*/
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#define __sanitize_fcr31(next) \
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do { \
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unsigned long fcr31 = mask_fcr31_x(next->thread.fpu.fcr31); \
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void __user *pc; \
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\
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if (unlikely(fcr31)) { \
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pc = (void __user *)task_pt_regs(next)->cp0_epc; \
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next->thread.fpu.fcr31 &= ~fcr31; \
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force_fcr31_sig(fcr31, pc, next); \
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} \
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} while (0)
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/*
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* For newly created kernel threads switch_to() will return to
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* ret_from_kernel_thread, newly created user threads to ret_from_fork.
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* That is, everything following resume() will be skipped for new threads.
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* So everything that matters to new threads should be placed before resume().
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*/
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#define switch_to(prev, next, last) \
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do { \
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__mips_mt_fpaff_switch_to(prev); \
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lose_fpu_inatomic(1, prev); \
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if (tsk_used_math(next)) \
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__sanitize_fcr31(next); \
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if (cpu_has_dsp) { \
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__save_dsp(prev); \
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__restore_dsp(next); \
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} \
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if (cop2_present) { \
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set_c0_status(ST0_CU2); \
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if ((KSTK_STATUS(prev) & ST0_CU2)) { \
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if (cop2_lazy_restore) \
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KSTK_STATUS(prev) &= ~ST0_CU2; \
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cop2_save(prev); \
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} \
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if (KSTK_STATUS(next) & ST0_CU2 && \
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!cop2_lazy_restore) { \
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cop2_restore(next); \
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} \
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clear_c0_status(ST0_CU2); \
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} \
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__clear_r6_hw_ll_bit(); \
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__clear_software_ll_bit(); \
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if (cpu_has_userlocal) \
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write_c0_userlocal(task_thread_info(next)->tp_value); \
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__restore_watch(next); \
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(last) = resume(prev, next, task_thread_info(next)); \
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} while (0)
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#endif /* _ASM_SWITCH_TO_H */
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