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aefc7f9a02
The PM1B registers are mirrors of the PM1A registers with different bits actually implemented. From the ACPI specification: "Although the bits can be split between the two register blocks (each register block has a unique pointer within the FADT), the bit positions are maintained. The register block with unimplemented bits (that is, those implemented in the other register block) always returns zeros, and writes have no side effects" Signed-off-by: Bob Moore <robert.moore@intel.com> Signed-off-by: Lin Ming <ming.m.lin@intel.com> Signed-off-by: Len Brown <len.brown@intel.com>
435 lines
12 KiB
C
435 lines
12 KiB
C
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/*******************************************************************************
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*
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* Module Name: hwregs - Read/write access functions for the various ACPI
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* control and status registers.
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*
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******************************************************************************/
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/*
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* Copyright (C) 2000 - 2008, Intel Corp.
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions, and the following disclaimer,
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* without modification.
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* 2. Redistributions in binary form must reproduce at minimum a disclaimer
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* substantially similar to the "NO WARRANTY" disclaimer below
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* ("Disclaimer") and any redistribution must be conditioned upon
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* including a substantially similar Disclaimer requirement for further
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* binary redistribution.
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* 3. Neither the names of the above-listed copyright holders nor the names
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* of any contributors may be used to endorse or promote products derived
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* from this software without specific prior written permission.
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*
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* Alternatively, this software may be distributed under the terms of the
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* GNU General Public License ("GPL") version 2 as published by the Free
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* Software Foundation.
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*
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* NO WARRANTY
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR
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* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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* HOLDERS OR CONTRIBUTORS BE LIABLE FOR SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
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* STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
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* IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGES.
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*/
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#include <acpi/acpi.h>
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#include "accommon.h"
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#include "acnamesp.h"
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#include "acevents.h"
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#define _COMPONENT ACPI_HARDWARE
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ACPI_MODULE_NAME("hwregs")
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/* Local Prototypes */
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static acpi_status
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acpi_hw_read_multiple(u32 *value,
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struct acpi_generic_address *register_a,
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struct acpi_generic_address *register_b);
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static acpi_status
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acpi_hw_write_multiple(u32 value,
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struct acpi_generic_address *register_a,
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struct acpi_generic_address *register_b);
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/*******************************************************************************
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*
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* FUNCTION: acpi_hw_clear_acpi_status
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*
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* PARAMETERS: None
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*
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* RETURN: Status
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*
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* DESCRIPTION: Clears all fixed and general purpose status bits
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*
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******************************************************************************/
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acpi_status acpi_hw_clear_acpi_status(void)
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{
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acpi_status status;
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acpi_cpu_flags lock_flags = 0;
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ACPI_FUNCTION_TRACE(hw_clear_acpi_status);
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ACPI_DEBUG_PRINT((ACPI_DB_IO, "About to write %04X to %0llX\n",
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ACPI_BITMASK_ALL_FIXED_STATUS,
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acpi_gbl_xpm1a_status.address));
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lock_flags = acpi_os_acquire_lock(acpi_gbl_hardware_lock);
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/* Clear the fixed events in PM1 A/B */
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status = acpi_hw_register_write(ACPI_REGISTER_PM1_STATUS,
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ACPI_BITMASK_ALL_FIXED_STATUS);
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if (ACPI_FAILURE(status)) {
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goto unlock_and_exit;
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}
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/* Clear the GPE Bits in all GPE registers in all GPE blocks */
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status = acpi_ev_walk_gpe_list(acpi_hw_clear_gpe_block, NULL);
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unlock_and_exit:
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acpi_os_release_lock(acpi_gbl_hardware_lock, lock_flags);
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return_ACPI_STATUS(status);
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}
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/*******************************************************************************
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*
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* FUNCTION: acpi_hw_get_register_bit_mask
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*
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* PARAMETERS: register_id - Index of ACPI Register to access
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*
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* RETURN: The bitmask to be used when accessing the register
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*
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* DESCRIPTION: Map register_id into a register bitmask.
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*
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******************************************************************************/
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struct acpi_bit_register_info *acpi_hw_get_bit_register_info(u32 register_id)
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{
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ACPI_FUNCTION_ENTRY();
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if (register_id > ACPI_BITREG_MAX) {
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ACPI_ERROR((AE_INFO, "Invalid BitRegister ID: %X",
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register_id));
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return (NULL);
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}
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return (&acpi_gbl_bit_register_info[register_id]);
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}
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/******************************************************************************
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*
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* FUNCTION: acpi_hw_register_read
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*
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* PARAMETERS: register_id - ACPI Register ID
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* return_value - Where the register value is returned
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*
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* RETURN: Status and the value read.
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*
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* DESCRIPTION: Read from the specified ACPI register
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*
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******************************************************************************/
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acpi_status
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acpi_hw_register_read(u32 register_id, u32 * return_value)
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{
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u32 value = 0;
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acpi_status status;
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ACPI_FUNCTION_TRACE(hw_register_read);
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switch (register_id) {
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case ACPI_REGISTER_PM1_STATUS: /* PM1 A/B: 16-bit access each */
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status = acpi_hw_read_multiple(&value,
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&acpi_gbl_xpm1a_status,
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&acpi_gbl_xpm1b_status);
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break;
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case ACPI_REGISTER_PM1_ENABLE: /* PM1 A/B: 16-bit access each */
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status = acpi_hw_read_multiple(&value,
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&acpi_gbl_xpm1a_enable,
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&acpi_gbl_xpm1b_enable);
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break;
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case ACPI_REGISTER_PM1_CONTROL: /* PM1 A/B: 16-bit access each */
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status = acpi_hw_read_multiple(&value,
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&acpi_gbl_FADT.
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xpm1a_control_block,
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&acpi_gbl_FADT.
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xpm1b_control_block);
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break;
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case ACPI_REGISTER_PM2_CONTROL: /* 8-bit access */
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status = acpi_read(&value, &acpi_gbl_FADT.xpm2_control_block);
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break;
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case ACPI_REGISTER_PM_TIMER: /* 32-bit access */
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status = acpi_read(&value, &acpi_gbl_FADT.xpm_timer_block);
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break;
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case ACPI_REGISTER_SMI_COMMAND_BLOCK: /* 8-bit access */
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status =
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acpi_os_read_port(acpi_gbl_FADT.smi_command, &value, 8);
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break;
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default:
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ACPI_ERROR((AE_INFO, "Unknown Register ID: %X", register_id));
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status = AE_BAD_PARAMETER;
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break;
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}
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if (ACPI_SUCCESS(status)) {
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*return_value = value;
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}
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return_ACPI_STATUS(status);
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}
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/******************************************************************************
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*
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* FUNCTION: acpi_hw_register_write
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*
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* PARAMETERS: register_id - ACPI Register ID
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* Value - The value to write
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*
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* RETURN: Status
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*
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* DESCRIPTION: Write to the specified ACPI register
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*
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* NOTE: In accordance with the ACPI specification, this function automatically
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* preserves the value of the following bits, meaning that these bits cannot be
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* changed via this interface:
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*
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* PM1_CONTROL[0] = SCI_EN
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* PM1_CONTROL[9]
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* PM1_STATUS[11]
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*
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* ACPI References:
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* 1) Hardware Ignored Bits: When software writes to a register with ignored
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* bit fields, it preserves the ignored bit fields
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* 2) SCI_EN: OSPM always preserves this bit position
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*
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******************************************************************************/
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acpi_status acpi_hw_register_write(u32 register_id, u32 value)
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{
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acpi_status status;
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u32 read_value;
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ACPI_FUNCTION_TRACE(hw_register_write);
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switch (register_id) {
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case ACPI_REGISTER_PM1_STATUS: /* PM1 A/B: 16-bit access each */
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/* Perform a read first to preserve certain bits (per ACPI spec) */
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status = acpi_hw_read_multiple(&read_value,
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&acpi_gbl_xpm1a_status,
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&acpi_gbl_xpm1b_status);
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if (ACPI_FAILURE(status)) {
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goto exit;
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}
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/* Insert the bits to be preserved */
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ACPI_INSERT_BITS(value, ACPI_PM1_STATUS_PRESERVED_BITS,
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read_value);
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/* Now we can write the data */
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status = acpi_hw_write_multiple(value,
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&acpi_gbl_xpm1a_status,
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&acpi_gbl_xpm1b_status);
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break;
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case ACPI_REGISTER_PM1_ENABLE: /* PM1 A/B: 16-bit access */
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status = acpi_hw_write_multiple(value,
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&acpi_gbl_xpm1a_enable,
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&acpi_gbl_xpm1b_enable);
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break;
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case ACPI_REGISTER_PM1_CONTROL: /* PM1 A/B: 16-bit access each */
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/*
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* Perform a read first to preserve certain bits (per ACPI spec)
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* Note: This includes SCI_EN, we never want to change this bit
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*/
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status = acpi_hw_read_multiple(&read_value,
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&acpi_gbl_FADT.
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xpm1a_control_block,
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&acpi_gbl_FADT.
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xpm1b_control_block);
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if (ACPI_FAILURE(status)) {
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goto exit;
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}
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/* Insert the bits to be preserved */
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ACPI_INSERT_BITS(value, ACPI_PM1_CONTROL_PRESERVED_BITS,
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read_value);
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/* Now we can write the data */
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status = acpi_hw_write_multiple(value,
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&acpi_gbl_FADT.
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xpm1a_control_block,
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&acpi_gbl_FADT.
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xpm1b_control_block);
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break;
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case ACPI_REGISTER_PM1A_CONTROL: /* 16-bit access */
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status = acpi_write(value, &acpi_gbl_FADT.xpm1a_control_block);
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break;
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case ACPI_REGISTER_PM1B_CONTROL: /* 16-bit access */
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status = acpi_write(value, &acpi_gbl_FADT.xpm1b_control_block);
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break;
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case ACPI_REGISTER_PM2_CONTROL: /* 8-bit access */
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status = acpi_write(value, &acpi_gbl_FADT.xpm2_control_block);
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break;
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case ACPI_REGISTER_PM_TIMER: /* 32-bit access */
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status = acpi_write(value, &acpi_gbl_FADT.xpm_timer_block);
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break;
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case ACPI_REGISTER_SMI_COMMAND_BLOCK: /* 8-bit access */
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/* SMI_CMD is currently always in IO space */
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status =
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acpi_os_write_port(acpi_gbl_FADT.smi_command, value, 8);
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break;
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default:
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ACPI_ERROR((AE_INFO, "Unknown Register ID: %X", register_id));
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status = AE_BAD_PARAMETER;
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break;
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}
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exit:
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return_ACPI_STATUS(status);
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}
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/******************************************************************************
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*
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* FUNCTION: acpi_hw_read_multiple
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*
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* PARAMETERS: Value - Where the register value is returned
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* register_a - First ACPI register (required)
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* register_b - Second ACPI register (optional)
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*
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* RETURN: Status
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*
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* DESCRIPTION: Read from the specified two-part ACPI register (such as PM1 A/B)
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*
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******************************************************************************/
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static acpi_status
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acpi_hw_read_multiple(u32 *value,
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struct acpi_generic_address *register_a,
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struct acpi_generic_address *register_b)
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{
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u32 value_a = 0;
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u32 value_b = 0;
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acpi_status status;
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/* The first register is always required */
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status = acpi_read(&value_a, register_a);
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if (ACPI_FAILURE(status)) {
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return (status);
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}
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/* Second register is optional */
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if (register_b->address) {
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status = acpi_read(&value_b, register_b);
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if (ACPI_FAILURE(status)) {
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return (status);
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}
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}
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/*
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* OR the two return values together. No shifting or masking is necessary,
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* because of how the PM1 registers are defined in the ACPI specification:
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*
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* "Although the bits can be split between the two register blocks (each
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* register block has a unique pointer within the FADT), the bit positions
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* are maintained. The register block with unimplemented bits (that is,
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* those implemented in the other register block) always returns zeros,
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* and writes have no side effects"
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*/
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*value = (value_a | value_b);
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return (AE_OK);
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}
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/******************************************************************************
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*
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* FUNCTION: acpi_hw_write_multiple
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*
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* PARAMETERS: Value - The value to write
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* register_a - First ACPI register (required)
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* register_b - Second ACPI register (optional)
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*
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* RETURN: Status
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*
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* DESCRIPTION: Write to the specified two-part ACPI register (such as PM1 A/B)
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*
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******************************************************************************/
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static acpi_status
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acpi_hw_write_multiple(u32 value,
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struct acpi_generic_address *register_a,
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struct acpi_generic_address *register_b)
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{
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acpi_status status;
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/* The first register is always required */
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status = acpi_write(value, register_a);
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if (ACPI_FAILURE(status)) {
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return (status);
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}
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/*
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* Second register is optional
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*
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* No bit shifting or clearing is necessary, because of how the PM1
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* registers are defined in the ACPI specification:
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*
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* "Although the bits can be split between the two register blocks (each
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* register block has a unique pointer within the FADT), the bit positions
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* are maintained. The register block with unimplemented bits (that is,
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* those implemented in the other register block) always returns zeros,
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* and writes have no side effects"
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*/
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if (register_b->address) {
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status = acpi_write(value, register_b);
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}
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return (status);
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}
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