mirror of
https://github.com/AuxXxilium/linux_dsm_epyc7002.git
synced 2024-12-21 15:48:56 +07:00
b9085bcbf5
Common: Optional support for adding a small amount of polling on each HLT
instruction executed in the guest (or equivalent for other architectures).
This can improve latency up to 50% on some scenarios (e.g. O_DSYNC writes
or TCP_RR netperf tests). This also has to be enabled manually for now,
but the plan is to auto-tune this in the future.
ARM/ARM64: the highlights are support for GICv3 emulation and dirty page
tracking
s390: several optimizations and bugfixes. Also a first: a feature
exposed by KVM (UUID and long guest name in /proc/sysinfo) before
it is available in IBM's hypervisor! :)
MIPS: Bugfixes.
x86: Support for PML (page modification logging, a new feature in
Broadwell Xeons that speeds up dirty page tracking), nested virtualization
improvements (nested APICv---a nice optimization), usual round of emulation
fixes. There is also a new option to reduce latency of the TSC deadline
timer in the guest; this needs to be tuned manually.
Some commits are common between this pull and Catalin's; I see you
have already included his tree.
ARM has other conflicts where functions are added in the same place
by 3.19-rc and 3.20 patches. These are not large though, and entirely
within KVM.
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Merge tag 'for-linus' of git://git.kernel.org/pub/scm/virt/kvm/kvm
Pull KVM update from Paolo Bonzini:
"Fairly small update, but there are some interesting new features.
Common:
Optional support for adding a small amount of polling on each HLT
instruction executed in the guest (or equivalent for other
architectures). This can improve latency up to 50% on some
scenarios (e.g. O_DSYNC writes or TCP_RR netperf tests). This
also has to be enabled manually for now, but the plan is to
auto-tune this in the future.
ARM/ARM64:
The highlights are support for GICv3 emulation and dirty page
tracking
s390:
Several optimizations and bugfixes. Also a first: a feature
exposed by KVM (UUID and long guest name in /proc/sysinfo) before
it is available in IBM's hypervisor! :)
MIPS:
Bugfixes.
x86:
Support for PML (page modification logging, a new feature in
Broadwell Xeons that speeds up dirty page tracking), nested
virtualization improvements (nested APICv---a nice optimization),
usual round of emulation fixes.
There is also a new option to reduce latency of the TSC deadline
timer in the guest; this needs to be tuned manually.
Some commits are common between this pull and Catalin's; I see you
have already included his tree.
Powerpc:
Nothing yet.
The KVM/PPC changes will come in through the PPC maintainers,
because I haven't received them yet and I might end up being
offline for some part of next week"
* tag 'for-linus' of git://git.kernel.org/pub/scm/virt/kvm/kvm: (130 commits)
KVM: ia64: drop kvm.h from installed user headers
KVM: x86: fix build with !CONFIG_SMP
KVM: x86: emulate: correct page fault error code for NoWrite instructions
KVM: Disable compat ioctl for s390
KVM: s390: add cpu model support
KVM: s390: use facilities and cpu_id per KVM
KVM: s390/CPACF: Choose crypto control block format
s390/kernel: Update /proc/sysinfo file with Extended Name and UUID
KVM: s390: reenable LPP facility
KVM: s390: floating irqs: fix user triggerable endless loop
kvm: add halt_poll_ns module parameter
kvm: remove KVM_MMIO_SIZE
KVM: MIPS: Don't leak FPU/DSP to guest
KVM: MIPS: Disable HTW while in guest
KVM: nVMX: Enable nested posted interrupt processing
KVM: nVMX: Enable nested virtual interrupt delivery
KVM: nVMX: Enable nested apic register virtualization
KVM: nVMX: Make nested control MSRs per-cpu
KVM: nVMX: Enable nested virtualize x2apic mode
KVM: nVMX: Prepare for using hardware MSR bitmap
...
247 lines
5.8 KiB
C
247 lines
5.8 KiB
C
/*
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* Copyright (C) 2012 - Virtual Open Systems and Columbia University
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* Author: Christoffer Dall <c.dall@virtualopensystems.com>
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License, version 2, as
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* published by the Free Software Foundation.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
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*/
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#ifndef __ARM_KVM_EMULATE_H__
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#define __ARM_KVM_EMULATE_H__
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#include <linux/kvm_host.h>
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#include <asm/kvm_asm.h>
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#include <asm/kvm_mmio.h>
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#include <asm/kvm_arm.h>
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#include <asm/cputype.h>
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unsigned long *vcpu_reg(struct kvm_vcpu *vcpu, u8 reg_num);
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unsigned long *vcpu_spsr(struct kvm_vcpu *vcpu);
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bool kvm_condition_valid(struct kvm_vcpu *vcpu);
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void kvm_skip_instr(struct kvm_vcpu *vcpu, bool is_wide_instr);
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void kvm_inject_undefined(struct kvm_vcpu *vcpu);
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void kvm_inject_dabt(struct kvm_vcpu *vcpu, unsigned long addr);
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void kvm_inject_pabt(struct kvm_vcpu *vcpu, unsigned long addr);
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static inline void vcpu_reset_hcr(struct kvm_vcpu *vcpu)
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{
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vcpu->arch.hcr = HCR_GUEST_MASK;
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}
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static inline unsigned long vcpu_get_hcr(struct kvm_vcpu *vcpu)
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{
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return vcpu->arch.hcr;
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}
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static inline void vcpu_set_hcr(struct kvm_vcpu *vcpu, unsigned long hcr)
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{
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vcpu->arch.hcr = hcr;
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}
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static inline bool vcpu_mode_is_32bit(struct kvm_vcpu *vcpu)
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{
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return 1;
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}
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static inline unsigned long *vcpu_pc(struct kvm_vcpu *vcpu)
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{
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return &vcpu->arch.regs.usr_regs.ARM_pc;
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}
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static inline unsigned long *vcpu_cpsr(struct kvm_vcpu *vcpu)
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{
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return &vcpu->arch.regs.usr_regs.ARM_cpsr;
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}
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static inline void vcpu_set_thumb(struct kvm_vcpu *vcpu)
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{
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*vcpu_cpsr(vcpu) |= PSR_T_BIT;
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}
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static inline bool mode_has_spsr(struct kvm_vcpu *vcpu)
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{
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unsigned long cpsr_mode = vcpu->arch.regs.usr_regs.ARM_cpsr & MODE_MASK;
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return (cpsr_mode > USR_MODE && cpsr_mode < SYSTEM_MODE);
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}
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static inline bool vcpu_mode_priv(struct kvm_vcpu *vcpu)
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{
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unsigned long cpsr_mode = vcpu->arch.regs.usr_regs.ARM_cpsr & MODE_MASK;
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return cpsr_mode > USR_MODE;;
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}
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static inline u32 kvm_vcpu_get_hsr(struct kvm_vcpu *vcpu)
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{
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return vcpu->arch.fault.hsr;
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}
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static inline unsigned long kvm_vcpu_get_hfar(struct kvm_vcpu *vcpu)
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{
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return vcpu->arch.fault.hxfar;
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}
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static inline phys_addr_t kvm_vcpu_get_fault_ipa(struct kvm_vcpu *vcpu)
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{
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return ((phys_addr_t)vcpu->arch.fault.hpfar & HPFAR_MASK) << 8;
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}
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static inline unsigned long kvm_vcpu_get_hyp_pc(struct kvm_vcpu *vcpu)
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{
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return vcpu->arch.fault.hyp_pc;
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}
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static inline bool kvm_vcpu_dabt_isvalid(struct kvm_vcpu *vcpu)
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{
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return kvm_vcpu_get_hsr(vcpu) & HSR_ISV;
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}
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static inline bool kvm_vcpu_dabt_iswrite(struct kvm_vcpu *vcpu)
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{
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return kvm_vcpu_get_hsr(vcpu) & HSR_WNR;
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}
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static inline bool kvm_vcpu_dabt_issext(struct kvm_vcpu *vcpu)
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{
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return kvm_vcpu_get_hsr(vcpu) & HSR_SSE;
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}
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static inline int kvm_vcpu_dabt_get_rd(struct kvm_vcpu *vcpu)
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{
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return (kvm_vcpu_get_hsr(vcpu) & HSR_SRT_MASK) >> HSR_SRT_SHIFT;
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}
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static inline bool kvm_vcpu_dabt_isextabt(struct kvm_vcpu *vcpu)
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{
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return kvm_vcpu_get_hsr(vcpu) & HSR_DABT_EA;
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}
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static inline bool kvm_vcpu_dabt_iss1tw(struct kvm_vcpu *vcpu)
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{
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return kvm_vcpu_get_hsr(vcpu) & HSR_DABT_S1PTW;
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}
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/* Get Access Size from a data abort */
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static inline int kvm_vcpu_dabt_get_as(struct kvm_vcpu *vcpu)
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{
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switch ((kvm_vcpu_get_hsr(vcpu) >> 22) & 0x3) {
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case 0:
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return 1;
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case 1:
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return 2;
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case 2:
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return 4;
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default:
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kvm_err("Hardware is weird: SAS 0b11 is reserved\n");
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return -EFAULT;
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}
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}
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/* This one is not specific to Data Abort */
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static inline bool kvm_vcpu_trap_il_is32bit(struct kvm_vcpu *vcpu)
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{
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return kvm_vcpu_get_hsr(vcpu) & HSR_IL;
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}
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static inline u8 kvm_vcpu_trap_get_class(struct kvm_vcpu *vcpu)
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{
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return kvm_vcpu_get_hsr(vcpu) >> HSR_EC_SHIFT;
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}
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static inline bool kvm_vcpu_trap_is_iabt(struct kvm_vcpu *vcpu)
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{
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return kvm_vcpu_trap_get_class(vcpu) == HSR_EC_IABT;
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}
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static inline u8 kvm_vcpu_trap_get_fault(struct kvm_vcpu *vcpu)
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{
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return kvm_vcpu_get_hsr(vcpu) & HSR_FSC;
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}
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static inline u8 kvm_vcpu_trap_get_fault_type(struct kvm_vcpu *vcpu)
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{
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return kvm_vcpu_get_hsr(vcpu) & HSR_FSC_TYPE;
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}
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static inline u32 kvm_vcpu_hvc_get_imm(struct kvm_vcpu *vcpu)
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{
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return kvm_vcpu_get_hsr(vcpu) & HSR_HVC_IMM_MASK;
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}
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static inline unsigned long kvm_vcpu_get_mpidr_aff(struct kvm_vcpu *vcpu)
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{
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return vcpu->arch.cp15[c0_MPIDR] & MPIDR_HWID_BITMASK;
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}
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static inline void kvm_vcpu_set_be(struct kvm_vcpu *vcpu)
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{
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*vcpu_cpsr(vcpu) |= PSR_E_BIT;
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}
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static inline bool kvm_vcpu_is_be(struct kvm_vcpu *vcpu)
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{
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return !!(*vcpu_cpsr(vcpu) & PSR_E_BIT);
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}
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static inline unsigned long vcpu_data_guest_to_host(struct kvm_vcpu *vcpu,
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unsigned long data,
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unsigned int len)
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{
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if (kvm_vcpu_is_be(vcpu)) {
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switch (len) {
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case 1:
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return data & 0xff;
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case 2:
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return be16_to_cpu(data & 0xffff);
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default:
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return be32_to_cpu(data);
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}
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} else {
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switch (len) {
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case 1:
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return data & 0xff;
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case 2:
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return le16_to_cpu(data & 0xffff);
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default:
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return le32_to_cpu(data);
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}
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}
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}
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static inline unsigned long vcpu_data_host_to_guest(struct kvm_vcpu *vcpu,
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unsigned long data,
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unsigned int len)
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{
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if (kvm_vcpu_is_be(vcpu)) {
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switch (len) {
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case 1:
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return data & 0xff;
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case 2:
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return cpu_to_be16(data & 0xffff);
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default:
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return cpu_to_be32(data);
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}
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} else {
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switch (len) {
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case 1:
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return data & 0xff;
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case 2:
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return cpu_to_le16(data & 0xffff);
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default:
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return cpu_to_le32(data);
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}
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}
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}
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#endif /* __ARM_KVM_EMULATE_H__ */
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