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linux_dsm_epyc7002/arch/riscv/include/asm
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Jim Wilson b90edb3301
RISC-V: Add futex support. 
Here is an attempt to add the missing futex support.  I started with the MIPS
version of futex.h and modified it until I got it working.  I tested it on
a HiFive Unleashed running Fedora Core 29 using the fc29 4.15 version of the
kernel.  This was tested against the glibc testsuite, where it fixes 14 nptl
related testsuite failures.  That unfortunately only tests the cmpxchg support,
so I also used the testcase at the end of

    https://lwn.net/Articles/148830/

which tests the atomic_op functionality, except that it doesn't verify that
the operations are atomic, which they obviously are.  This testcase runs
successfully with the patch and fails without it.

I'm not a kernel expert, so there could be details I got wrong here.  I wasn't
sure about the memory model support, so I used aqrl which seemed safest, and
didn't add fences which seemed unnecessary.  I'm not sure about the copyright
statements, I left in Ralf Baechle's line because I started with his code.
Checkpatch reports some style problems, but it is the same style as the MIPS
futex.h, and the uses of ENOSYS appear correct even though it complains about
them.  I don't know if any of that matters.

This patch was tested on qemu with the glibc nptl/tst-cond-except
testcase, and the wake_op testcase from above.

Signed-off-by: Jim Wilson <jimw@sifive.com>
Reviewed-by: Christoph Hellwig <hch@lst.de>
Signed-off-by: Palmer Dabbelt <palmer@sifive.com>
2018-10-22 17:38:08 -07:00
..
asm-offsets.h RISC-V: Task implementation 2017-09-26 15:26:46 -07:00
asm-prototypes.h RISC-V: include linux/ftrace.h in asm-prototypes.h 2018-09-24 13:12:27 -07:00
asm.h RISC-V: use RISCV_{INT,SHORT} instead of {INT,SHORT} for asm macros 2017-11-30 10:01:10 -08:00
atomic.h locking/atomics: Rework ordering barriers 2018-07-25 11:53:59 +02:00
barrier.h riscv/barrier: Define __smp_{store_release,load_acquire} 2018-04-02 19:59:43 -07:00
bitops.h RISC-V: __test_and_op_bit_ord should be strongly ordered 2017-11-28 14:04:05 -08:00
bug.h RISC-V: use RISCV_{INT,SHORT} instead of {INT,SHORT} for asm macros 2017-11-30 10:01:10 -08:00
cache.h
cacheflush.h riscv: use NULL instead of a plain 0 2018-06-07 08:01:50 -07:00
cmpxchg.h riscv/atomic: Strengthen implementations with fences 2018-04-02 19:59:44 -07:00
csr.h RISC-V: add a definition for the SIE SEIE bit 2018-08-13 08:31:31 -07:00
current.h RISC-V: Task implementation 2017-09-26 15:26:46 -07:00
delay.h RISC-V: Device, timer, IRQs, and the SBI 2017-09-26 15:26:47 -07:00
dma-mapping.h riscv: add swiotlb support 2018-05-19 08:46:26 +02:00
elf.h RISC-V: ELF and module implementation 2017-09-26 15:26:46 -07:00
fence.h riscv/spinlock: Strengthen implementations with fences 2018-04-02 19:59:43 -07:00
ftrace.h riscv/ftrace: Add DYNAMIC_FTRACE_WITH_REGS support 2018-04-02 19:59:13 -07:00
futex.h RISC-V: Add futex support. 2018-10-22 17:38:08 -07:00
hwcap.h RISC-V: ELF and module implementation 2017-09-26 15:26:46 -07:00
io.h riscv: remove CONFIG_MMU ifdefs 2018-01-07 15:14:39 -08:00
irq.h RISC-V: remove INTERRUPT_CAUSE_* defines from asm/irq.h 2018-08-13 08:31:31 -07:00
irqflags.h riscv: rename SR_* constants to match the spec 2018-01-07 15:14:39 -08:00
Kbuild RISC-V: Add futex support. 2018-10-22 17:38:08 -07:00
kprobes.h RISC-V: Task implementation 2017-09-26 15:26:46 -07:00
linkage.h RISC-V: Generic library routines and assembly 2017-09-26 15:26:45 -07:00
mmu_context.h riscv: inline set_pgdir into its only caller 2018-01-30 19:16:17 -08:00
mmu.h RISC-V: Flush I$ when making a dirty page executable 2017-11-30 12:58:25 -08:00
module.h RISC-V: Add section of GOT.PLT for kernel module 2018-04-02 20:00:54 -07:00
page.h RISC-V: Paging and MMU 2017-09-26 15:26:47 -07:00
pci.h PCI: remove PCI_DMA_BUS_IS_PHYS 2018-05-07 07:15:41 +02:00
perf_event.h RISC-V: Fix !CONFIG_SMP compilation error 2018-08-13 08:31:32 -07:00
pgalloc.h RISC-V: Paging and MMU 2017-09-26 15:26:47 -07:00
pgtable-32.h RISC-V: Paging and MMU 2017-09-26 15:26:47 -07:00
pgtable-64.h RISC-V: Paging and MMU 2017-09-26 15:26:47 -07:00
pgtable-bits.h mm: introduce ARCH_HAS_PTE_SPECIAL 2018-06-07 17:34:35 -07:00
pgtable.h riscv: remove CONFIG_MMU ifdefs 2018-01-07 15:14:39 -08:00
processor.h RISC-V: Task implementation 2017-09-26 15:26:46 -07:00
ptrace.h riscv: rename SR_* constants to match the spec 2018-01-07 15:14:39 -08:00
sbi.h RISC-V: Device, timer, IRQs, and the SBI 2017-09-26 15:26:47 -07:00
smp.h clocksource: new RISC-V SBI timer driver 2018-08-13 08:31:31 -07:00
spinlock_types.h
spinlock.h riscv/spinlock: Strengthen implementations with fences 2018-04-02 19:59:43 -07:00
string.h RISC-V: Generic library routines and assembly 2017-09-26 15:26:45 -07:00
switch_to.h RISC-V: Task implementation 2017-09-26 15:26:46 -07:00
syscall.h RISC-V: User-facing API 2017-09-26 15:26:48 -07:00
thread_info.h Construct init thread stack in the linker script rather than by union 2018-01-09 23:21:02 +00:00
timex.h RISC-V: Use define for get_cycles like other architectures 2017-11-30 10:12:21 -08:00
tlb.h riscv: tlb: Provide definition of tlb_flush() before including tlb.h 2018-08-28 12:58:35 -07:00
tlbflush.h riscv: use NULL instead of a plain 0 2018-06-07 08:01:50 -07:00
uaccess.h riscv: split the declaration of __copy_user 2018-06-09 12:34:31 -07:00
unistd.h RISC-V: Don't use a global include guard for uapi/asm/syscalls.h 2018-08-20 10:55:24 -07:00
vdso.h RISC-V: Define sys_riscv_flush_icache when SMP=n 2018-08-20 10:55:24 -07:00
word-at-a-time.h RISC-V: Generic library routines and assembly 2017-09-26 15:26:45 -07:00