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https://github.com/AuxXxilium/linux_dsm_epyc7002.git
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aeec6cc082
When platform_clock_control() first selects PLL1 as sysclk the PLL_CTRL registers have not been setup yet and we effectively have an invalid clock configuration until byt_rt5651_aif1_hw_params() gets called. Add a new byt_rt5651_prepare_and_enable_pll1() helper and use that from both platform_clock_control() and byt_rt5651_aif1_hw_params() to fix this. Tested-by: Carlo Caione <carlo@endlessm.com> Signed-off-by: Hans de Goede <hdegoede@redhat.com> Signed-off-by: Mark Brown <broonie@kernel.org> |
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| .. | ||
| adi | ||
| amd | ||
| atmel | ||
| au1x | ||
| bcm | ||
| blackfin | ||
| cirrus | ||
| codecs | ||
| davinci | ||
| dwc | ||
| fsl | ||
| generic | ||
| hisilicon | ||
| img | ||
| intel | ||
| jz4740 | ||
| kirkwood | ||
| mediatek | ||
| mxs | ||
| nuc900 | ||
| omap | ||
| pxa | ||
| qcom | ||
| rockchip | ||
| samsung | ||
| sh | ||
| sirf | ||
| spear | ||
| sti | ||
| stm | ||
| sunxi | ||
| tegra | ||
| txx9 | ||
| uniphier | ||
| ux500 | ||
| xtensa | ||
| zte | ||
| Kconfig | ||
| Makefile | ||
| soc-ac97.c | ||
| soc-acpi.c | ||
| soc-cache.c | ||
| soc-compress.c | ||
| soc-core.c | ||
| soc-dapm.c | ||
| soc-devres.c | ||
| soc-generic-dmaengine-pcm.c | ||
| soc-io.c | ||
| soc-jack.c | ||
| soc-ops.c | ||
| soc-pcm.c | ||
| soc-topology.c | ||
| soc-utils.c | ||