..
dcn20_dccg.c
drm/amd/display: Formula refactor for calculating DPP CLK DTO
2019-12-18 16:09:10 -05:00
dcn20_dccg.h
drm/amd/display: Revert fixup DPP programming sequence
2019-10-03 09:10:51 -05:00
dcn20_dpp_cm.c
drm/amd/display: Indirect reg read macro with shift and mask
2020-01-16 14:13:53 -05:00
dcn20_dpp.c
drm/amd/display: dcn20: remove an unused function
2020-03-09 13:50:39 -04:00
dcn20_dpp.h
drm/amd/display: Indirect reg read macro with shift and mask
2020-01-16 14:13:53 -05:00
dcn20_dsc.c
drm/amd/display: fix image corruption with ODM 2:1 DSC 2 slice
2020-03-05 00:29:57 -05:00
dcn20_dsc.h
drm/amd/display: Drop CONFIG_DRM_AMD_DC_DCN2_0 and DSC_SUPPORTED
2019-11-13 15:29:44 -05:00
dcn20_dwb_scl.c
drm/amd/display: Remove set but not used variables 'h_ratio_chroma', 'v_ratio_chroma'
2019-10-07 15:10:43 -05:00
dcn20_dwb.c
dcn20_dwb.h
dcn20_hubbub.c
drm/amd/display: optimize prgoram wm and clks
2020-02-25 11:09:37 -05:00
dcn20_hubbub.h
drm/amd/display: Add detile buffer size for DCN20
2019-10-03 09:10:58 -05:00
dcn20_hubp.c
drm/amd/display: Wrong ifdef guards were used around DML validation
2019-12-05 16:27:16 -05:00
dcn20_hubp.h
drm/amd/display: Drop CONFIG_DRM_AMD_DC_DCN2_1 flag
2019-11-13 15:29:44 -05:00
dcn20_hwseq.c
drm/amd/display: Program DSC during timing programming
2020-03-09 13:49:34 -04:00
dcn20_hwseq.h
drm/amd/display: Added locking for atomic update stream and update planes
2020-02-06 15:04:37 -05:00
dcn20_init.c
drm/amd/display: Add function pointers for panel related hw functions
2020-02-25 11:05:35 -05:00
dcn20_init.h
drm/amd/display: cleanup of function pointer tables
2019-11-19 10:12:53 -05:00
dcn20_link_encoder.c
drm/amd/display: Drop CONFIG_DRM_AMD_DC_DCN2_0 and DSC_SUPPORTED
2019-11-13 15:29:44 -05:00
dcn20_link_encoder.h
drm/amd/display: add missing dcn link encoder regs
2019-12-18 16:09:06 -05:00
dcn20_mmhubbub.c
dcn20_mmhubbub.h
drm/amd/display: Update register defines
2020-02-11 11:50:18 -05:00
dcn20_mpc.c
drm/amd/display: Indirect reg read macro with shift and mask
2020-01-16 14:13:53 -05:00
dcn20_mpc.h
drm/amd/display: Indirect reg read macro with shift and mask
2020-01-16 14:13:53 -05:00
dcn20_opp.c
drm/amd/display: program DPG_OFFSET_SEGMENT for odm_pipe
2020-03-05 00:29:47 -05:00
dcn20_opp.h
drm/amd/display: program DPG_OFFSET_SEGMENT for odm_pipe
2020-03-05 00:29:47 -05:00
dcn20_optc.c
drm/amd/display: Fix manual trigger source for DCN2
2019-12-18 16:09:10 -05:00
dcn20_optc.h
drm/amd/display: Fix manual trigger source for DCN2
2019-12-18 16:09:10 -05:00
dcn20_resource.c
drm/amd/display: update soc bb for nv14
2020-03-09 13:48:38 -04:00
dcn20_resource.h
drm/amd/display: add worst case dcc meta pitch to fake plane
2020-03-05 00:29:13 -05:00
dcn20_stream_encoder.c
drm/amd/display: add stream_enc_inst for PSP HDCP inst use
2020-02-06 15:04:37 -05:00
dcn20_stream_encoder.h
drm/amd/display: set MSA MISC1 bit 6 while sending colorimetry in VSC SDP
2019-11-13 15:29:43 -05:00
dcn20_vmid.c
drm/amd/display: Poll for GPUVM context ready (v2)
2019-07-18 14:18:09 -05:00
dcn20_vmid.h
drm/amd/display: Update register defines
2020-02-11 11:50:18 -05:00
Makefile
amdgpu: Enable initial DCN support on POWER
2019-12-18 16:09:05 -05:00