Per Fransson ae6948048c ARM: ux500 specific L2 cache code ... The generic version of l2x0_inv_all is only called just after disabling the L2 cache and is surrounded by a spinlock. However, we're not really turning off the L2 cache right now, and the PL310 does not support exclusive accesses (used to implement the spinlock). So, the invalidation needs to be done without the spinlock. Cc: Thomas Gleixner <tglx@linutronix.de> Cc: Catalin Marinas <catalin.marinas@arm.com> Cc: Hans-Juergen Koch <hjk@linutronix.de> Cc: Santosh Shilimkar <santosh.shilimkar@ti.com> Signed-off-by: Per Fransson <per.xx.fransson@stericsson.com> Signed-off-by: Linus Walleij <linus.walleij@stericsson.com>		2010-10-26 11:40:06 +05:30
..
include/mach	Merge branch 'next' of git://git.kernel.org/pub/scm/linux/kernel/git/djbw/async_tx	2010-08-09 21:00:07 -07:00
board-mop500.c	ARM: 6267/1: mop500: add AB8500 interrupt support	2010-07-27 08:28:32 +01:00
board-u5500.c
clock.c	ARM: AMBA: Add pclk definition for platforms using primecells	2010-07-22 09:55:38 +01:00
clock.h
cpu-db5500.c	ARM: 6184/2: ux500: use neutral PRCMU base	2010-07-09 14:46:47 +01:00
cpu-db8500.c
cpu.c	ARM: ux500 specific L2 cache code	2010-10-26 11:40:06 +05:30
devices-db5500.c
devices-db8500.c	Merge branch 'next' of git://git.kernel.org/pub/scm/linux/kernel/git/djbw/async_tx	2010-08-09 21:00:07 -07:00
devices.c
headsmp.S
Kconfig
localtimer.c
Makefile	ARM: 6152/1: ux500 make it possible to disable localtimers	2010-06-08 19:25:49 +01:00
Makefile.boot
pins-db8500.h	ARM: 6160/1: ux500: add DB8500 pin configs	2010-06-16 22:30:48 +01:00
platsmp.c
ste-dma40-db8500.h	DMAENGINE: ste_dma40: add DB8500 memcpy channels	2010-06-22 18:01:56 -07:00