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https://github.com/AuxXxilium/linux_dsm_epyc7002.git
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ae2eca724a
Add code to deal with instruction, data and branch caches of the V4e ColdFire cores when they are running with the MMU enabled. This code is loosely based on Freescales changes for the caches of the V4e ColdFire in the 2.6.25 kernel BSP. That code was originally by Kurt Mahan <kmahan@freescale.com> (now <kmahan@xmission.com>). Signed-off-by: Greg Ungerer <gerg@uclinux.org> Acked-by: Geert Uytterhoeven <geert@linux-m68k.org> Acked-by: Matt Waddel <mwaddel@yahoo.com> Acked-by: Kurt Mahan <kmahan@xmission.com>
137 lines
3.3 KiB
C
137 lines
3.3 KiB
C
/*
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* linux/arch/m68k/mm/cache.c
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*
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* Instruction cache handling
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*
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* Copyright (C) 1995 Hamish Macdonald
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*/
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#include <linux/module.h>
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#include <asm/pgalloc.h>
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#include <asm/traps.h>
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static unsigned long virt_to_phys_slow(unsigned long vaddr)
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{
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if (CPU_IS_060) {
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unsigned long paddr;
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/* The PLPAR instruction causes an access error if the translation
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* is not possible. To catch this we use the same exception mechanism
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* as for user space accesses in <asm/uaccess.h>. */
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asm volatile (".chip 68060\n"
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"1: plpar (%0)\n"
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".chip 68k\n"
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"2:\n"
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".section .fixup,\"ax\"\n"
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" .even\n"
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"3: sub.l %0,%0\n"
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" jra 2b\n"
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".previous\n"
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".section __ex_table,\"a\"\n"
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" .align 4\n"
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" .long 1b,3b\n"
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".previous"
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: "=a" (paddr)
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: "0" (vaddr));
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return paddr;
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} else if (CPU_IS_040) {
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unsigned long mmusr;
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asm volatile (".chip 68040\n\t"
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"ptestr (%1)\n\t"
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"movec %%mmusr, %0\n\t"
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".chip 68k"
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: "=r" (mmusr)
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: "a" (vaddr));
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if (mmusr & MMU_R_040)
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return (mmusr & PAGE_MASK) | (vaddr & ~PAGE_MASK);
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} else {
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unsigned short mmusr;
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unsigned long *descaddr;
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asm volatile ("ptestr %3,%2@,#7,%0\n\t"
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"pmove %%psr,%1@"
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: "=a&" (descaddr)
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: "a" (&mmusr), "a" (vaddr), "d" (get_fs().seg));
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if (mmusr & (MMU_I|MMU_B|MMU_L))
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return 0;
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descaddr = phys_to_virt((unsigned long)descaddr);
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switch (mmusr & MMU_NUM) {
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case 1:
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return (*descaddr & 0xfe000000) | (vaddr & 0x01ffffff);
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case 2:
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return (*descaddr & 0xfffc0000) | (vaddr & 0x0003ffff);
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case 3:
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return (*descaddr & PAGE_MASK) | (vaddr & ~PAGE_MASK);
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}
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}
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return 0;
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}
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/* Push n pages at kernel virtual address and clear the icache */
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/* RZ: use cpush %bc instead of cpush %dc, cinv %ic */
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void flush_icache_range(unsigned long address, unsigned long endaddr)
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{
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if (CPU_IS_COLDFIRE) {
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unsigned long start, end;
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start = address & ICACHE_SET_MASK;
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end = endaddr & ICACHE_SET_MASK;
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if (start > end) {
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flush_cf_icache(0, end);
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end = ICACHE_MAX_ADDR;
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}
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flush_cf_icache(start, end);
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} else if (CPU_IS_040_OR_060) {
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address &= PAGE_MASK;
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do {
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asm volatile ("nop\n\t"
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".chip 68040\n\t"
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"cpushp %%bc,(%0)\n\t"
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".chip 68k"
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: : "a" (virt_to_phys_slow(address)));
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address += PAGE_SIZE;
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} while (address < endaddr);
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} else {
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unsigned long tmp;
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asm volatile ("movec %%cacr,%0\n\t"
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"orw %1,%0\n\t"
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"movec %0,%%cacr"
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: "=&d" (tmp)
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: "di" (FLUSH_I));
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}
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}
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EXPORT_SYMBOL(flush_icache_range);
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void flush_icache_user_range(struct vm_area_struct *vma, struct page *page,
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unsigned long addr, int len)
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{
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if (CPU_IS_COLDFIRE) {
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unsigned long start, end;
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start = addr & ICACHE_SET_MASK;
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end = (addr + len) & ICACHE_SET_MASK;
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if (start > end) {
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flush_cf_icache(0, end);
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end = ICACHE_MAX_ADDR;
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}
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flush_cf_icache(start, end);
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} else if (CPU_IS_040_OR_060) {
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asm volatile ("nop\n\t"
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".chip 68040\n\t"
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"cpushp %%bc,(%0)\n\t"
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".chip 68k"
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: : "a" (page_to_phys(page)));
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} else {
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unsigned long tmp;
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asm volatile ("movec %%cacr,%0\n\t"
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"orw %1,%0\n\t"
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"movec %0,%%cacr"
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: "=&d" (tmp)
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: "di" (FLUSH_I));
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}
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}
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