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94d0e5980d
Architecturally, TLBs are private to the (physical) CPU they're associated with. But when multiple vcpus from the same VM are being multiplexed on the same CPU, the TLBs are not private to the vcpus (and are actually shared across the VMID). Let's consider the following scenario: - vcpu-0 maps PA to VA - vcpu-1 maps PA' to VA If run on the same physical CPU, vcpu-1 can hit TLB entries generated by vcpu-0 accesses, and access the wrong physical page. The solution to this is to keep a per-VM map of which vcpu ran last on each given physical CPU, and invalidate local TLBs when switching to a different vcpu from the same VM. Reviewed-by: Christoffer Dall <christoffer.dall@linaro.org> Signed-off-by: Marc Zyngier <marc.zyngier@arm.com>
79 lines
2.0 KiB
C
79 lines
2.0 KiB
C
/*
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* Original code:
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* Copyright (C) 2012 - Virtual Open Systems and Columbia University
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* Author: Christoffer Dall <c.dall@virtualopensystems.com>
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*
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* Mostly rewritten in C by Marc Zyngier <marc.zyngier@arm.com>
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program. If not, see <http://www.gnu.org/licenses/>.
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*/
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#include <asm/kvm_hyp.h>
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/**
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* Flush per-VMID TLBs
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*
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* __kvm_tlb_flush_vmid(struct kvm *kvm);
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*
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* We rely on the hardware to broadcast the TLB invalidation to all CPUs
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* inside the inner-shareable domain (which is the case for all v7
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* implementations). If we come across a non-IS SMP implementation, we'll
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* have to use an IPI based mechanism. Until then, we stick to the simple
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* hardware assisted version.
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*
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* As v7 does not support flushing per IPA, just nuke the whole TLB
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* instead, ignoring the ipa value.
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*/
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void __hyp_text __kvm_tlb_flush_vmid(struct kvm *kvm)
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{
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dsb(ishst);
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/* Switch to requested VMID */
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kvm = kern_hyp_va(kvm);
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write_sysreg(kvm->arch.vttbr, VTTBR);
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isb();
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write_sysreg(0, TLBIALLIS);
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dsb(ish);
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isb();
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write_sysreg(0, VTTBR);
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}
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void __hyp_text __kvm_tlb_flush_vmid_ipa(struct kvm *kvm, phys_addr_t ipa)
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{
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__kvm_tlb_flush_vmid(kvm);
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}
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void __hyp_text __kvm_tlb_flush_local_vmid(struct kvm_vcpu *vcpu)
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{
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struct kvm *kvm = kern_hyp_va(kern_hyp_va(vcpu)->kvm);
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/* Switch to requested VMID */
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write_sysreg(kvm->arch.vttbr, VTTBR);
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isb();
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write_sysreg(0, TLBIALL);
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dsb(nsh);
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isb();
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write_sysreg(0, VTTBR);
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}
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void __hyp_text __kvm_flush_vm_context(void)
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{
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write_sysreg(0, TLBIALLNSNHIS);
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write_sysreg(0, ICIALLUIS);
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dsb(ish);
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}
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