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https://github.com/AuxXxilium/linux_dsm_epyc7002.git
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f95a2b3d98
RK2928 and RK3066 contain a dw_apb timer component, while the rk3188 uses a slightly similar but still different timer component. But all of them support the ARM-global-timer that got added as clocksource driver recently. So enable support for it to get a working clocksource for rk3188. Signed-off-by: Heiko Stuebner <heiko@sntech.de>
125 lines
3.0 KiB
Plaintext
125 lines
3.0 KiB
Plaintext
/*
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* Copyright (c) 2013 MundoReader S.L.
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* Author: Heiko Stuebner <heiko@sntech.de>
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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#include <dt-bindings/interrupt-controller/irq.h>
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#include <dt-bindings/interrupt-controller/arm-gic.h>
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#include "skeleton.dtsi"
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/ {
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interrupt-parent = <&gic>;
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soc {
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#address-cells = <1>;
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#size-cells = <1>;
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compatible = "simple-bus";
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ranges;
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gic: interrupt-controller@1013d000 {
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compatible = "arm,cortex-a9-gic";
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interrupt-controller;
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#interrupt-cells = <3>;
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reg = <0x1013d000 0x1000>,
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<0x1013c100 0x0100>;
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};
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L2: l2-cache-controller@10138000 {
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compatible = "arm,pl310-cache";
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reg = <0x10138000 0x1000>;
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cache-unified;
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cache-level = <2>;
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};
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global-timer@1013c200 {
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compatible = "arm,cortex-a9-global-timer";
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reg = <0x1013c200 0x20>;
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interrupts = <GIC_PPI 11 0x304>;
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clocks = <&dummy150m>;
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};
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local-timer@1013c600 {
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compatible = "arm,cortex-a9-twd-timer";
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reg = <0x1013c600 0x20>;
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interrupts = <GIC_PPI 13 0x304>;
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clocks = <&dummy150m>;
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};
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uart0: serial@10124000 {
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compatible = "snps,dw-apb-uart";
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reg = <0x10124000 0x400>;
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interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
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reg-shift = <2>;
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reg-io-width = <1>;
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clocks = <&clk_gates1 8>;
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status = "disabled";
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};
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uart1: serial@10126000 {
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compatible = "snps,dw-apb-uart";
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reg = <0x10126000 0x400>;
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interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
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reg-shift = <2>;
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reg-io-width = <1>;
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clocks = <&clk_gates1 10>;
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status = "disabled";
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};
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uart2: serial@20064000 {
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compatible = "snps,dw-apb-uart";
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reg = <0x20064000 0x400>;
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interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
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reg-shift = <2>;
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reg-io-width = <1>;
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clocks = <&clk_gates1 12>;
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status = "disabled";
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};
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uart3: serial@20068000 {
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compatible = "snps,dw-apb-uart";
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reg = <0x20068000 0x400>;
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interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
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reg-shift = <2>;
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reg-io-width = <1>;
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clocks = <&clk_gates1 14>;
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status = "disabled";
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};
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dwmmc@10214000 {
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compatible = "rockchip,rk2928-dw-mshc";
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reg = <0x10214000 0x1000>;
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interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
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#address-cells = <1>;
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#size-cells = <0>;
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clocks = <&clk_gates5 10>, <&clk_gates2 11>;
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clock-names = "biu", "ciu";
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status = "disabled";
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};
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dwmmc@10218000 {
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compatible = "rockchip,rk2928-dw-mshc";
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reg = <0x10218000 0x1000>;
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interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
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#address-cells = <1>;
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#size-cells = <0>;
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clocks = <&clk_gates5 11>, <&clk_gates2 13>;
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clock-names = "biu", "ciu";
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status = "disabled";
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};
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};
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};
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