linux_dsm_epyc7002/arch/mips/include/asm/smp-ops.h
Paul Burton e83f7e02af MIPS: CPS: Have asm/mips-cps.h include CM & CPC headers
With Coherence Manager (CM) 3.5 information about the topology of the
system, which has previously only been available through & accessed from
the CM, is now also provided by the Cluster Power Controller (CPC). This
includes a new CPC_CONFIG register mirroring GCR_CONFIG, and similarly a
new CPC_Cx_CONFIG register mirroring GCR_Cx_CONFIG.

In preparation for adjusting functions such as mips_cm_numcores(), which
have previously only needed to access the CM, to also access the CPC
this patch modifies the way we use the various CPS headers. Rather than
having users include asm/mips-cm.h or asm/mips-cpc.h individually we
instead have users include asm/mips-cps.h which in turn includes
asm/mips-cm.h & asm/mips-cpc.h. This means that users will gain access
to both CM & CPC registers by including one header, and most importantly
it makes asm/mips-cps.h an ideal location for helper functions which
need to access the various components of the CPS.

Signed-off-by: Paul Burton <paul.burton@imgtec.com>
Cc: linux-mips@linux-mips.org
Patchwork: https://patchwork.linux-mips.org/patch/17015/
Patchwork: https://patchwork.linux-mips.org/patch/17217/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2017-08-30 00:57:27 +02:00

118 lines
2.3 KiB
C

/*
* This file is subject to the terms and conditions of the GNU General
* Public License. See the file "COPYING" in the main directory of this
* archive for more details.
*
* Copyright (C) 2000 - 2001 by Kanoj Sarcar (kanoj@sgi.com)
* Copyright (C) 2000 - 2001 by Silicon Graphics, Inc.
* Copyright (C) 2000, 2001, 2002 Ralf Baechle
* Copyright (C) 2000, 2001 Broadcom Corporation
*/
#ifndef __ASM_SMP_OPS_H
#define __ASM_SMP_OPS_H
#include <linux/errno.h>
#include <asm/mips-cps.h>
#ifdef CONFIG_SMP
#include <linux/cpumask.h>
struct task_struct;
struct plat_smp_ops {
void (*send_ipi_single)(int cpu, unsigned int action);
void (*send_ipi_mask)(const struct cpumask *mask, unsigned int action);
void (*init_secondary)(void);
void (*smp_finish)(void);
int (*boot_secondary)(int cpu, struct task_struct *idle);
void (*smp_setup)(void);
void (*prepare_cpus)(unsigned int max_cpus);
#ifdef CONFIG_HOTPLUG_CPU
int (*cpu_disable)(void);
void (*cpu_die)(unsigned int cpu);
#endif
};
extern void register_smp_ops(const struct plat_smp_ops *ops);
static inline void plat_smp_setup(void)
{
extern const struct plat_smp_ops *mp_ops; /* private */
mp_ops->smp_setup();
}
extern void mips_smp_send_ipi_single(int cpu, unsigned int action);
extern void mips_smp_send_ipi_mask(const struct cpumask *mask,
unsigned int action);
#else /* !CONFIG_SMP */
struct plat_smp_ops;
static inline void plat_smp_setup(void)
{
/* UP, nothing to do ... */
}
static inline void register_smp_ops(const struct plat_smp_ops *ops)
{
}
#endif /* !CONFIG_SMP */
static inline int register_up_smp_ops(void)
{
#ifdef CONFIG_SMP_UP
extern const struct plat_smp_ops up_smp_ops;
register_smp_ops(&up_smp_ops);
return 0;
#else
return -ENODEV;
#endif
}
static inline int register_cmp_smp_ops(void)
{
#ifdef CONFIG_MIPS_CMP
extern const struct plat_smp_ops cmp_smp_ops;
if (!mips_cm_present())
return -ENODEV;
register_smp_ops(&cmp_smp_ops);
return 0;
#else
return -ENODEV;
#endif
}
static inline int register_vsmp_smp_ops(void)
{
#ifdef CONFIG_MIPS_MT_SMP
extern const struct plat_smp_ops vsmp_smp_ops;
register_smp_ops(&vsmp_smp_ops);
return 0;
#else
return -ENODEV;
#endif
}
#ifdef CONFIG_MIPS_CPS
extern int register_cps_smp_ops(void);
#else
static inline int register_cps_smp_ops(void)
{
return -ENODEV;
}
#endif
#endif /* __ASM_SMP_OPS_H */