mirror of
https://github.com/AuxXxilium/linux_dsm_epyc7002.git
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2b8b15da66
PWM devices can be referenced in the DT by phandle and per-chip index. In order for this to work properly, the PWM controller needs to have a label attached to it. Signed-off-by: Thierry Reding <thierry.reding@avionic-design.de> Signed-off-by: Stephen Warren <swarren@nvidia.com>
278 lines
6.0 KiB
Plaintext
278 lines
6.0 KiB
Plaintext
/include/ "skeleton.dtsi"
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/ {
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compatible = "nvidia,tegra30";
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interrupt-parent = <&intc>;
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intc: interrupt-controller {
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compatible = "arm,cortex-a9-gic";
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reg = <0x50041000 0x1000
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0x50040100 0x0100>;
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interrupt-controller;
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#interrupt-cells = <3>;
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};
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apbdma: dma {
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compatible = "nvidia,tegra30-apbdma", "nvidia,tegra20-apbdma";
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reg = <0x6000a000 0x1400>;
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interrupts = <0 104 0x04
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0 105 0x04
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0 106 0x04
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0 107 0x04
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0 108 0x04
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0 109 0x04
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0 110 0x04
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0 111 0x04
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0 112 0x04
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0 113 0x04
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0 114 0x04
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0 115 0x04
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0 116 0x04
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0 117 0x04
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0 118 0x04
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0 119 0x04
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0 128 0x04
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0 129 0x04
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0 130 0x04
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0 131 0x04
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0 132 0x04
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0 133 0x04
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0 134 0x04
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0 135 0x04
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0 136 0x04
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0 137 0x04
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0 138 0x04
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0 139 0x04
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0 140 0x04
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0 141 0x04
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0 142 0x04
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0 143 0x04>;
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};
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ahb: ahb {
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compatible = "nvidia,tegra30-ahb";
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reg = <0x6000c004 0x14c>; /* AHB Arbitration + Gizmo Controller */
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};
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gpio: gpio {
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compatible = "nvidia,tegra30-gpio", "nvidia,tegra20-gpio";
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reg = <0x6000d000 0x1000>;
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interrupts = <0 32 0x04
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0 33 0x04
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0 34 0x04
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0 35 0x04
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0 55 0x04
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0 87 0x04
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0 89 0x04
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0 125 0x04>;
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#gpio-cells = <2>;
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gpio-controller;
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#interrupt-cells = <2>;
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interrupt-controller;
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};
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pinmux: pinmux {
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compatible = "nvidia,tegra30-pinmux";
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reg = <0x70000868 0xd0 /* Pad control registers */
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0x70003000 0x3e0>; /* Mux registers */
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};
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serial@70006000 {
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compatible = "nvidia,tegra30-uart", "nvidia,tegra20-uart";
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reg = <0x70006000 0x40>;
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reg-shift = <2>;
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interrupts = <0 36 0x04>;
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status = "disabled";
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};
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serial@70006040 {
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compatible = "nvidia,tegra30-uart", "nvidia,tegra20-uart";
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reg = <0x70006040 0x40>;
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reg-shift = <2>;
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interrupts = <0 37 0x04>;
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status = "disabled";
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};
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serial@70006200 {
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compatible = "nvidia,tegra30-uart", "nvidia,tegra20-uart";
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reg = <0x70006200 0x100>;
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reg-shift = <2>;
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interrupts = <0 46 0x04>;
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status = "disabled";
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};
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serial@70006300 {
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compatible = "nvidia,tegra30-uart", "nvidia,tegra20-uart";
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reg = <0x70006300 0x100>;
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reg-shift = <2>;
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interrupts = <0 90 0x04>;
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status = "disabled";
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};
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serial@70006400 {
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compatible = "nvidia,tegra30-uart", "nvidia,tegra20-uart";
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reg = <0x70006400 0x100>;
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reg-shift = <2>;
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interrupts = <0 91 0x04>;
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status = "disabled";
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};
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pwm: pwm {
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compatible = "nvidia,tegra30-pwm", "nvidia,tegra20-pwm";
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reg = <0x7000a000 0x100>;
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#pwm-cells = <2>;
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};
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i2c@7000c000 {
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compatible = "nvidia,tegra30-i2c", "nvidia,tegra20-i2c";
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reg = <0x7000c000 0x100>;
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interrupts = <0 38 0x04>;
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#address-cells = <1>;
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#size-cells = <0>;
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status = "disabled";
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};
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i2c@7000c400 {
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compatible = "nvidia,tegra30-i2c", "nvidia,tegra20-i2c";
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reg = <0x7000c400 0x100>;
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interrupts = <0 84 0x04>;
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#address-cells = <1>;
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#size-cells = <0>;
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status = "disabled";
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};
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i2c@7000c500 {
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compatible = "nvidia,tegra30-i2c", "nvidia,tegra20-i2c";
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reg = <0x7000c500 0x100>;
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interrupts = <0 92 0x04>;
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#address-cells = <1>;
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#size-cells = <0>;
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status = "disabled";
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};
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i2c@7000c700 {
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compatible = "nvidia,tegra30-i2c", "nvidia,tegra20-i2c";
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reg = <0x7000c700 0x100>;
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interrupts = <0 120 0x04>;
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#address-cells = <1>;
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#size-cells = <0>;
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status = "disabled";
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};
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i2c@7000d000 {
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compatible = "nvidia,tegra30-i2c", "nvidia,tegra20-i2c";
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reg = <0x7000d000 0x100>;
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interrupts = <0 53 0x04>;
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#address-cells = <1>;
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#size-cells = <0>;
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status = "disabled";
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};
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pmc {
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compatible = "nvidia,tegra20-pmc", "nvidia,tegra30-pmc";
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reg = <0x7000e400 0x400>;
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};
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memory-controller {
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compatible = "nvidia,tegra30-mc";
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reg = <0x7000f000 0x010
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0x7000f03c 0x1b4
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0x7000f200 0x028
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0x7000f284 0x17c>;
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interrupts = <0 77 0x04>;
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};
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smmu {
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compatible = "nvidia,tegra30-smmu";
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reg = <0x7000f010 0x02c
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0x7000f1f0 0x010
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0x7000f228 0x05c>;
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nvidia,#asids = <4>; /* # of ASIDs */
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dma-window = <0 0x40000000>; /* IOVA start & length */
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nvidia,ahb = <&ahb>;
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};
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ahub {
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compatible = "nvidia,tegra30-ahub";
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reg = <0x70080000 0x200
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0x70080200 0x100>;
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interrupts = <0 103 0x04>;
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nvidia,dma-request-selector = <&apbdma 1>;
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ranges;
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#address-cells = <1>;
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#size-cells = <1>;
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tegra_i2s0: i2s@70080300 {
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compatible = "nvidia,tegra30-i2s";
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reg = <0x70080300 0x100>;
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nvidia,ahub-cif-ids = <4 4>;
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status = "disabled";
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};
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tegra_i2s1: i2s@70080400 {
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compatible = "nvidia,tegra30-i2s";
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reg = <0x70080400 0x100>;
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nvidia,ahub-cif-ids = <5 5>;
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status = "disabled";
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};
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tegra_i2s2: i2s@70080500 {
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compatible = "nvidia,tegra30-i2s";
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reg = <0x70080500 0x100>;
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nvidia,ahub-cif-ids = <6 6>;
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status = "disabled";
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};
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tegra_i2s3: i2s@70080600 {
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compatible = "nvidia,tegra30-i2s";
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reg = <0x70080600 0x100>;
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nvidia,ahub-cif-ids = <7 7>;
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status = "disabled";
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};
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tegra_i2s4: i2s@70080700 {
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compatible = "nvidia,tegra30-i2s";
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reg = <0x70080700 0x100>;
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nvidia,ahub-cif-ids = <8 8>;
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status = "disabled";
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};
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};
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sdhci@78000000 {
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compatible = "nvidia,tegra30-sdhci", "nvidia,tegra20-sdhci";
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reg = <0x78000000 0x200>;
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interrupts = <0 14 0x04>;
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status = "disabled";
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};
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sdhci@78000200 {
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compatible = "nvidia,tegra30-sdhci", "nvidia,tegra20-sdhci";
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reg = <0x78000200 0x200>;
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interrupts = <0 15 0x04>;
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status = "disabled";
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};
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sdhci@78000400 {
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compatible = "nvidia,tegra30-sdhci", "nvidia,tegra20-sdhci";
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reg = <0x78000400 0x200>;
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interrupts = <0 19 0x04>;
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status = "disabled";
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};
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sdhci@78000600 {
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compatible = "nvidia,tegra30-sdhci", "nvidia,tegra20-sdhci";
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reg = <0x78000600 0x200>;
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interrupts = <0 31 0x04>;
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status = "disabled";
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};
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pmu {
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compatible = "arm,cortex-a9-pmu";
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interrupts = <0 144 0x04
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0 145 0x04
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0 146 0x04
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0 147 0x04>;
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};
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};
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