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Based on 2 normalized pattern(s): this program is free software you can redistribute it and or modify it under the terms of the gnu general public license version 2 as this program is free software you can redistribute it and or modify it under the terms of the gnu general public license version 2 as publishhed by the free software foundation extracted by the scancode license scanner the SPDX license identifier GPL-2.0-only has been chosen to replace the boilerplate/reference in 48 file(s). Signed-off-by: Thomas Gleixner <tglx@linutronix.de> Reviewed-by: Alexios Zavras <alexios.zavras@intel.com> Reviewed-by: Kate Stewart <kstewart@linuxfoundation.org> Reviewed-by: Allison Randal <allison@lohutok.net> Cc: linux-spdx@vger.kernel.org Link: https://lkml.kernel.org/r/20190530000436.292339952@linutronix.de Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
109 lines
3.0 KiB
Plaintext
109 lines
3.0 KiB
Plaintext
// SPDX-License-Identifier: GPL-2.0-only
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/*
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* Copyright (C) 2014 STMicroelectronics Limited.
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* Author: Peter Griffin <peter.griffin@linaro.org>
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*/
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#include "stih418-clock.dtsi"
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#include "stih407-family.dtsi"
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#include "stih410-pinctrl.dtsi"
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/ {
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cpus {
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#address-cells = <1>;
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#size-cells = <0>;
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cpu@2 {
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device_type = "cpu";
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compatible = "arm,cortex-a9";
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reg = <2>;
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/* u-boot puts hpen in SBC dmem at 0xa4 offset */
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cpu-release-addr = <0x94100A4>;
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};
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cpu@3 {
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device_type = "cpu";
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compatible = "arm,cortex-a9";
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reg = <3>;
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/* u-boot puts hpen in SBC dmem at 0xa4 offset */
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cpu-release-addr = <0x94100A4>;
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};
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};
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soc {
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usb2_picophy1: phy2@0 {
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compatible = "st,stih407-usb2-phy";
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reg = <0 0>;
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#phy-cells = <0>;
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st,syscfg = <&syscfg_core 0xf8 0xf4>;
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resets = <&softreset STIH407_PICOPHY_SOFTRESET>,
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<&picophyreset STIH407_PICOPHY0_RESET>;
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reset-names = "global", "port";
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};
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usb2_picophy2: phy3@0 {
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compatible = "st,stih407-usb2-phy";
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reg = <0 0>;
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#phy-cells = <0>;
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st,syscfg = <&syscfg_core 0xfc 0xf4>;
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resets = <&softreset STIH407_PICOPHY_SOFTRESET>,
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<&picophyreset STIH407_PICOPHY1_RESET>;
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reset-names = "global", "port";
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};
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ohci0: usb@9a03c00 {
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compatible = "st,st-ohci-300x";
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reg = <0x9a03c00 0x100>;
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interrupts = <GIC_SPI 180 IRQ_TYPE_NONE>;
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clocks = <&clk_s_c0_flexgen CLK_TX_ICN_DISP_0>;
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resets = <&powerdown STIH407_USB2_PORT0_POWERDOWN>,
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<&softreset STIH407_USB2_PORT0_SOFTRESET>;
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reset-names = "power", "softreset";
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phys = <&usb2_picophy1>;
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phy-names = "usb";
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};
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ehci0: usb@9a03e00 {
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compatible = "st,st-ehci-300x";
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reg = <0x9a03e00 0x100>;
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interrupts = <GIC_SPI 151 IRQ_TYPE_NONE>;
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_usb0>;
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clocks = <&clk_s_c0_flexgen CLK_TX_ICN_DISP_0>;
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resets = <&powerdown STIH407_USB2_PORT0_POWERDOWN>,
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<&softreset STIH407_USB2_PORT0_SOFTRESET>;
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reset-names = "power", "softreset";
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phys = <&usb2_picophy1>;
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phy-names = "usb";
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};
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ohci1: usb@9a83c00 {
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compatible = "st,st-ohci-300x";
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reg = <0x9a83c00 0x100>;
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interrupts = <GIC_SPI 181 IRQ_TYPE_NONE>;
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clocks = <&clk_s_c0_flexgen CLK_TX_ICN_DISP_0>;
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resets = <&powerdown STIH407_USB2_PORT1_POWERDOWN>,
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<&softreset STIH407_USB2_PORT1_SOFTRESET>;
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reset-names = "power", "softreset";
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phys = <&usb2_picophy2>;
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phy-names = "usb";
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};
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ehci1: usb@9a83e00 {
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compatible = "st,st-ehci-300x";
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reg = <0x9a83e00 0x100>;
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interrupts = <GIC_SPI 153 IRQ_TYPE_NONE>;
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_usb1>;
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clocks = <&clk_s_c0_flexgen CLK_TX_ICN_DISP_0>;
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resets = <&powerdown STIH407_USB2_PORT1_POWERDOWN>,
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<&softreset STIH407_USB2_PORT1_SOFTRESET>;
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reset-names = "power", "softreset";
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phys = <&usb2_picophy2>;
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phy-names = "usb";
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};
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mmc0: sdhci@9060000 {
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assigned-clocks = <&clk_s_c0_flexgen CLK_MMC_0>;
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assigned-clock-parents = <&clk_s_c0_pll1 0>;
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assigned-clock-rates = <200000000>;
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};
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};
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};
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