mirror of
https://github.com/AuxXxilium/linux_dsm_epyc7002.git
synced 2024-12-22 00:37:52 +07:00
19d52e94e0
This series of changes mostly configures the cameras for dra7 and am437x that have been pending for few months now because of waiting for clock dependencies to clear. So these changes are based on earlier dts changes with with Tero Kristo's for-5.6-ti-clk branch merged in. Then there's a series of changes to configure powervr sgx target module for am335x, am437x and dra7 that have been waiting to have the rstctrl reset driver dependencies to clear. Also included are few minor patches to configure 1-wire and coulomb counter calibration interrupt for droid4. -----BEGIN PGP SIGNATURE----- iQJFBAABCAAvFiEEkgNvrZJU/QSQYIcQG9Q+yVyrpXMFAl4rTjIRHHRvbnlAYXRv bWlkZS5jb20ACgkQG9Q+yVyrpXNPIxAAsx6cR/yzoEvUv1fGFi44Y/VZEhfI/8yT 5esGWql/UINkyTLBTsME6liDTt7rAVxcHH1JQj04hYH/w/PQU8S4iu8ZVwxoAb9R Mmnfn8Py26scney0zseJc6tTTDbtXF+mxDBYUqAJNKjDyoRkJKxWtMMOHUC7WjVW P5E4uWgi2ydEFgn6hOzLORgHPtNnOWPdXYzKvmum7VZdRny7KHcuOk4kVFnj3dzG RwGrsOQcs2EyHd08n+U3tZqk34JqhOWi2VAKPZTHVlsZOdDKU9hm45ZSDh/j7Xoy 74x2ux81guKBAtgpKSJR5TUottgPM5IdnnyCmKkDgF7AWySByeJYPOVWyxwZuSQD tCmCi9fFSXCogoijMvSFPbcsKI/u6UKHYIOS9zvJo70FxNVTckhzjTH+DRQpjrTB oEAfpCS56bHUUYvPomDvxRT87kLlcs/A6g8+puRKd2xa3dmsXkTKeppuEBIC6WKE JtZYGsvWSe0gSVscsrE3Ecf17jS2O7Yhy3/4eOHJzUgsIGn8xcjuJJO3Av+bFj87 kDF66tRKR6LcKD1S6v5a87hmKD3rxkj23LUEvS0bWsOVLmgqIQYeZYpR5ujkRLxC 1NlzWFVqBtCMe6qPRz7FaitrdZlTaMURRD0GXSQmZCsTrSVrghUTJBZw92ep2kWD rIwSzpB1p08= =u4PK -----END PGP SIGNATURE----- Merge tag 'omap-for-v5.6/dt-late-signed' of git://git.kernel.org/pub/scm/linux/kernel/git/tmlind/linux-omap into arm/late Late omap dts changes for v5.6 merge window This series of changes mostly configures the cameras for dra7 and am437x that have been pending for few months now because of waiting for clock dependencies to clear. So these changes are based on earlier dts changes with with Tero Kristo's for-5.6-ti-clk branch merged in. Then there's a series of changes to configure powervr sgx target module for am335x, am437x and dra7 that have been waiting to have the rstctrl reset driver dependencies to clear. Also included are few minor patches to configure 1-wire and coulomb counter calibration interrupt for droid4. * tag 'omap-for-v5.6/dt-late-signed' of git://git.kernel.org/pub/scm/linux/kernel/git/tmlind/linux-omap: (25 commits) ARM: dts: omap4-droid4: Enable hdq for droid4 ds250x 1-wire battery nvmem ARM: dts: motorola-cpcap-mapphone: Configure calibration interrupt ARM: dts: Configure interconnect target module for am437x sgx ARM: dts: Configure sgx for dra7 ARM: dts: Configure rstctrl reset for am335x SGX ARM: dts: dra7: Add ti-sysc node for VPE ARM: dts: dra7: add vpe clkctrl node ARM: dts: am43x-epos-evm: Add VPFE and OV2659 entries ARM: dts: am437x-sk-evm: Add VPFE and OV2659 entries ARM: dts: am43xx: add support for clkout1 clock arm: dts: dra76-evm: Add CAL and OV5640 nodes arm: dtsi: dra76x: Add CAL dtsi node arm: dts: dra72-evm-common: Add entries for the CSI2 cameras ARM: dts: DRA72: Add CAL dtsi node ARM: dts: dra7-l4: Add ti-sysc node for CAM ARM: OMAP: DRA7xx: Make CAM clock domain SWSUP only ARM: dts: dra7: add cam clkctrl node ARM: dts: Add omap3-echo ARM: dts: Add dtsi files for AM3703, AM3715 and DM3725 ARM: dts: am335x-icev2: Add support for OSD9616P0899-10 at i2c0 ... Link: https://lore.kernel.org/r/pull-1579896427-50330@atomide.com-3 Signed-off-by: Olof Johansson <olof@lixom.net>
555 lines
13 KiB
Plaintext
555 lines
13 KiB
Plaintext
/*
|
|
* Device Tree Source for AM33XX SoC
|
|
*
|
|
* Copyright (C) 2012 Texas Instruments Incorporated - http://www.ti.com/
|
|
*
|
|
* This file is licensed under the terms of the GNU General Public License
|
|
* version 2. This program is licensed "as is" without any warranty of any
|
|
* kind, whether express or implied.
|
|
*/
|
|
|
|
#include <dt-bindings/bus/ti-sysc.h>
|
|
#include <dt-bindings/gpio/gpio.h>
|
|
#include <dt-bindings/pinctrl/am33xx.h>
|
|
#include <dt-bindings/clock/am3.h>
|
|
|
|
/ {
|
|
compatible = "ti,am33xx";
|
|
interrupt-parent = <&intc>;
|
|
#address-cells = <1>;
|
|
#size-cells = <1>;
|
|
chosen { };
|
|
|
|
aliases {
|
|
i2c0 = &i2c0;
|
|
i2c1 = &i2c1;
|
|
i2c2 = &i2c2;
|
|
serial0 = &uart0;
|
|
serial1 = &uart1;
|
|
serial2 = &uart2;
|
|
serial3 = &uart3;
|
|
serial4 = &uart4;
|
|
serial5 = &uart5;
|
|
d-can0 = &dcan0;
|
|
d-can1 = &dcan1;
|
|
usb0 = &usb0;
|
|
usb1 = &usb1;
|
|
phy0 = &usb0_phy;
|
|
phy1 = &usb1_phy;
|
|
ethernet0 = &cpsw_emac0;
|
|
ethernet1 = &cpsw_emac1;
|
|
spi0 = &spi0;
|
|
spi1 = &spi1;
|
|
};
|
|
|
|
cpus {
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
cpu@0 {
|
|
compatible = "arm,cortex-a8";
|
|
device_type = "cpu";
|
|
reg = <0>;
|
|
|
|
operating-points-v2 = <&cpu0_opp_table>;
|
|
|
|
clocks = <&dpll_mpu_ck>;
|
|
clock-names = "cpu";
|
|
|
|
clock-latency = <300000>; /* From omap-cpufreq driver */
|
|
};
|
|
};
|
|
|
|
cpu0_opp_table: opp-table {
|
|
compatible = "operating-points-v2-ti-cpu";
|
|
syscon = <&scm_conf>;
|
|
|
|
/*
|
|
* The three following nodes are marked with opp-suspend
|
|
* because the can not be enabled simultaneously on a
|
|
* single SoC.
|
|
*/
|
|
opp50-300000000 {
|
|
opp-hz = /bits/ 64 <300000000>;
|
|
opp-microvolt = <950000 931000 969000>;
|
|
opp-supported-hw = <0x06 0x0010>;
|
|
opp-suspend;
|
|
};
|
|
|
|
opp100-275000000 {
|
|
opp-hz = /bits/ 64 <275000000>;
|
|
opp-microvolt = <1100000 1078000 1122000>;
|
|
opp-supported-hw = <0x01 0x00FF>;
|
|
opp-suspend;
|
|
};
|
|
|
|
opp100-300000000 {
|
|
opp-hz = /bits/ 64 <300000000>;
|
|
opp-microvolt = <1100000 1078000 1122000>;
|
|
opp-supported-hw = <0x06 0x0020>;
|
|
opp-suspend;
|
|
};
|
|
|
|
opp100-500000000 {
|
|
opp-hz = /bits/ 64 <500000000>;
|
|
opp-microvolt = <1100000 1078000 1122000>;
|
|
opp-supported-hw = <0x01 0xFFFF>;
|
|
};
|
|
|
|
opp100-600000000 {
|
|
opp-hz = /bits/ 64 <600000000>;
|
|
opp-microvolt = <1100000 1078000 1122000>;
|
|
opp-supported-hw = <0x06 0x0040>;
|
|
};
|
|
|
|
opp120-600000000 {
|
|
opp-hz = /bits/ 64 <600000000>;
|
|
opp-microvolt = <1200000 1176000 1224000>;
|
|
opp-supported-hw = <0x01 0xFFFF>;
|
|
};
|
|
|
|
opp120-720000000 {
|
|
opp-hz = /bits/ 64 <720000000>;
|
|
opp-microvolt = <1200000 1176000 1224000>;
|
|
opp-supported-hw = <0x06 0x0080>;
|
|
};
|
|
|
|
oppturbo-720000000 {
|
|
opp-hz = /bits/ 64 <720000000>;
|
|
opp-microvolt = <1260000 1234800 1285200>;
|
|
opp-supported-hw = <0x01 0xFFFF>;
|
|
};
|
|
|
|
oppturbo-800000000 {
|
|
opp-hz = /bits/ 64 <800000000>;
|
|
opp-microvolt = <1260000 1234800 1285200>;
|
|
opp-supported-hw = <0x06 0x0100>;
|
|
};
|
|
|
|
oppnitro-1000000000 {
|
|
opp-hz = /bits/ 64 <1000000000>;
|
|
opp-microvolt = <1325000 1298500 1351500>;
|
|
opp-supported-hw = <0x04 0x0200>;
|
|
};
|
|
};
|
|
|
|
pmu@4b000000 {
|
|
compatible = "arm,cortex-a8-pmu";
|
|
interrupts = <3>;
|
|
reg = <0x4b000000 0x1000000>;
|
|
ti,hwmods = "debugss";
|
|
};
|
|
|
|
/*
|
|
* The soc node represents the soc top level view. It is used for IPs
|
|
* that are not memory mapped in the MPU view or for the MPU itself.
|
|
*/
|
|
soc {
|
|
compatible = "ti,omap-infra";
|
|
mpu {
|
|
compatible = "ti,omap3-mpu";
|
|
ti,hwmods = "mpu";
|
|
pm-sram = <&pm_sram_code
|
|
&pm_sram_data>;
|
|
};
|
|
};
|
|
|
|
/*
|
|
* XXX: Use a flat representation of the AM33XX interconnect.
|
|
* The real AM33XX interconnect network is quite complex. Since
|
|
* it will not bring real advantage to represent that in DT
|
|
* for the moment, just use a fake OCP bus entry to represent
|
|
* the whole bus hierarchy.
|
|
*/
|
|
ocp {
|
|
compatible = "simple-bus";
|
|
#address-cells = <1>;
|
|
#size-cells = <1>;
|
|
ranges;
|
|
ti,hwmods = "l3_main";
|
|
|
|
l4_wkup: interconnect@44c00000 {
|
|
wkup_m3: wkup_m3@100000 {
|
|
compatible = "ti,am3352-wkup-m3";
|
|
reg = <0x100000 0x4000>,
|
|
<0x180000 0x2000>;
|
|
reg-names = "umem", "dmem";
|
|
ti,hwmods = "wkup_m3";
|
|
ti,pm-firmware = "am335x-pm-firmware.elf";
|
|
};
|
|
};
|
|
l4_per: interconnect@48000000 {
|
|
};
|
|
l4_fw: interconnect@47c00000 {
|
|
};
|
|
l4_fast: interconnect@4a000000 {
|
|
};
|
|
l4_mpuss: interconnect@4b140000 {
|
|
};
|
|
|
|
intc: interrupt-controller@48200000 {
|
|
compatible = "ti,am33xx-intc";
|
|
interrupt-controller;
|
|
#interrupt-cells = <1>;
|
|
reg = <0x48200000 0x1000>;
|
|
};
|
|
|
|
edma: edma@49000000 {
|
|
compatible = "ti,edma3-tpcc";
|
|
ti,hwmods = "tpcc";
|
|
reg = <0x49000000 0x10000>;
|
|
reg-names = "edma3_cc";
|
|
interrupts = <12 13 14>;
|
|
interrupt-names = "edma3_ccint", "edma3_mperr",
|
|
"edma3_ccerrint";
|
|
dma-requests = <64>;
|
|
#dma-cells = <2>;
|
|
|
|
ti,tptcs = <&edma_tptc0 7>, <&edma_tptc1 5>,
|
|
<&edma_tptc2 0>;
|
|
|
|
ti,edma-memcpy-channels = <20 21>;
|
|
};
|
|
|
|
edma_tptc0: tptc@49800000 {
|
|
compatible = "ti,edma3-tptc";
|
|
ti,hwmods = "tptc0";
|
|
reg = <0x49800000 0x100000>;
|
|
interrupts = <112>;
|
|
interrupt-names = "edma3_tcerrint";
|
|
};
|
|
|
|
edma_tptc1: tptc@49900000 {
|
|
compatible = "ti,edma3-tptc";
|
|
ti,hwmods = "tptc1";
|
|
reg = <0x49900000 0x100000>;
|
|
interrupts = <113>;
|
|
interrupt-names = "edma3_tcerrint";
|
|
};
|
|
|
|
edma_tptc2: tptc@49a00000 {
|
|
compatible = "ti,edma3-tptc";
|
|
ti,hwmods = "tptc2";
|
|
reg = <0x49a00000 0x100000>;
|
|
interrupts = <114>;
|
|
interrupt-names = "edma3_tcerrint";
|
|
};
|
|
|
|
target-module@47810000 {
|
|
compatible = "ti,sysc-omap2", "ti,sysc";
|
|
reg = <0x478102fc 0x4>,
|
|
<0x47810110 0x4>,
|
|
<0x47810114 0x4>;
|
|
reg-names = "rev", "sysc", "syss";
|
|
ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY |
|
|
SYSC_OMAP2_ENAWAKEUP |
|
|
SYSC_OMAP2_SOFTRESET |
|
|
SYSC_OMAP2_AUTOIDLE)>;
|
|
ti,sysc-sidle = <SYSC_IDLE_FORCE>,
|
|
<SYSC_IDLE_NO>,
|
|
<SYSC_IDLE_SMART>;
|
|
ti,syss-mask = <1>;
|
|
clocks = <&l3s_clkctrl AM3_L3S_MMC3_CLKCTRL 0>;
|
|
clock-names = "fck";
|
|
#address-cells = <1>;
|
|
#size-cells = <1>;
|
|
ranges = <0x0 0x47810000 0x1000>;
|
|
|
|
mmc3: mmc@0 {
|
|
compatible = "ti,omap4-hsmmc";
|
|
ti,needs-special-reset;
|
|
interrupts = <29>;
|
|
reg = <0x0 0x1000>;
|
|
};
|
|
};
|
|
|
|
usb: target-module@47400000 {
|
|
compatible = "ti,sysc-omap4", "ti,sysc";
|
|
reg = <0x47400000 0x4>,
|
|
<0x47400010 0x4>;
|
|
reg-names = "rev", "sysc";
|
|
ti,sysc-mask = <(SYSC_OMAP4_FREEEMU |
|
|
SYSC_OMAP2_SOFTRESET)>;
|
|
ti,sysc-midle = <SYSC_IDLE_FORCE>,
|
|
<SYSC_IDLE_NO>,
|
|
<SYSC_IDLE_SMART>;
|
|
ti,sysc-sidle = <SYSC_IDLE_FORCE>,
|
|
<SYSC_IDLE_NO>,
|
|
<SYSC_IDLE_SMART>,
|
|
<SYSC_IDLE_SMART_WKUP>;
|
|
clocks = <&l3s_clkctrl AM3_L3S_USB_OTG_HS_CLKCTRL 0>;
|
|
clock-names = "fck";
|
|
#address-cells = <1>;
|
|
#size-cells = <1>;
|
|
ranges = <0x0 0x47400000 0x5000>;
|
|
|
|
usb0_phy: usb-phy@1300 {
|
|
compatible = "ti,am335x-usb-phy";
|
|
reg = <0x1300 0x100>;
|
|
reg-names = "phy";
|
|
ti,ctrl_mod = <&usb_ctrl_mod>;
|
|
#phy-cells = <0>;
|
|
};
|
|
|
|
usb0: usb@1400 {
|
|
compatible = "ti,musb-am33xx";
|
|
reg = <0x1400 0x400>,
|
|
<0x1000 0x200>;
|
|
reg-names = "mc", "control";
|
|
|
|
interrupts = <18>;
|
|
interrupt-names = "mc";
|
|
dr_mode = "otg";
|
|
mentor,multipoint = <1>;
|
|
mentor,num-eps = <16>;
|
|
mentor,ram-bits = <12>;
|
|
mentor,power = <500>;
|
|
phys = <&usb0_phy>;
|
|
|
|
dmas = <&cppi41dma 0 0 &cppi41dma 1 0
|
|
&cppi41dma 2 0 &cppi41dma 3 0
|
|
&cppi41dma 4 0 &cppi41dma 5 0
|
|
&cppi41dma 6 0 &cppi41dma 7 0
|
|
&cppi41dma 8 0 &cppi41dma 9 0
|
|
&cppi41dma 10 0 &cppi41dma 11 0
|
|
&cppi41dma 12 0 &cppi41dma 13 0
|
|
&cppi41dma 14 0 &cppi41dma 0 1
|
|
&cppi41dma 1 1 &cppi41dma 2 1
|
|
&cppi41dma 3 1 &cppi41dma 4 1
|
|
&cppi41dma 5 1 &cppi41dma 6 1
|
|
&cppi41dma 7 1 &cppi41dma 8 1
|
|
&cppi41dma 9 1 &cppi41dma 10 1
|
|
&cppi41dma 11 1 &cppi41dma 12 1
|
|
&cppi41dma 13 1 &cppi41dma 14 1>;
|
|
dma-names =
|
|
"rx1", "rx2", "rx3", "rx4", "rx5", "rx6", "rx7",
|
|
"rx8", "rx9", "rx10", "rx11", "rx12", "rx13",
|
|
"rx14", "rx15",
|
|
"tx1", "tx2", "tx3", "tx4", "tx5", "tx6", "tx7",
|
|
"tx8", "tx9", "tx10", "tx11", "tx12", "tx13",
|
|
"tx14", "tx15";
|
|
};
|
|
|
|
usb1_phy: usb-phy@1b00 {
|
|
compatible = "ti,am335x-usb-phy";
|
|
reg = <0x1b00 0x100>;
|
|
reg-names = "phy";
|
|
ti,ctrl_mod = <&usb_ctrl_mod>;
|
|
#phy-cells = <0>;
|
|
};
|
|
|
|
usb1: usb@1800 {
|
|
compatible = "ti,musb-am33xx";
|
|
reg = <0x1c00 0x400>,
|
|
<0x1800 0x200>;
|
|
reg-names = "mc", "control";
|
|
interrupts = <19>;
|
|
interrupt-names = "mc";
|
|
dr_mode = "otg";
|
|
mentor,multipoint = <1>;
|
|
mentor,num-eps = <16>;
|
|
mentor,ram-bits = <12>;
|
|
mentor,power = <500>;
|
|
phys = <&usb1_phy>;
|
|
|
|
dmas = <&cppi41dma 15 0 &cppi41dma 16 0
|
|
&cppi41dma 17 0 &cppi41dma 18 0
|
|
&cppi41dma 19 0 &cppi41dma 20 0
|
|
&cppi41dma 21 0 &cppi41dma 22 0
|
|
&cppi41dma 23 0 &cppi41dma 24 0
|
|
&cppi41dma 25 0 &cppi41dma 26 0
|
|
&cppi41dma 27 0 &cppi41dma 28 0
|
|
&cppi41dma 29 0 &cppi41dma 15 1
|
|
&cppi41dma 16 1 &cppi41dma 17 1
|
|
&cppi41dma 18 1 &cppi41dma 19 1
|
|
&cppi41dma 20 1 &cppi41dma 21 1
|
|
&cppi41dma 22 1 &cppi41dma 23 1
|
|
&cppi41dma 24 1 &cppi41dma 25 1
|
|
&cppi41dma 26 1 &cppi41dma 27 1
|
|
&cppi41dma 28 1 &cppi41dma 29 1>;
|
|
dma-names =
|
|
"rx1", "rx2", "rx3", "rx4", "rx5", "rx6", "rx7",
|
|
"rx8", "rx9", "rx10", "rx11", "rx12", "rx13",
|
|
"rx14", "rx15",
|
|
"tx1", "tx2", "tx3", "tx4", "tx5", "tx6", "tx7",
|
|
"tx8", "tx9", "tx10", "tx11", "tx12", "tx13",
|
|
"tx14", "tx15";
|
|
};
|
|
|
|
cppi41dma: dma-controller@2000 {
|
|
compatible = "ti,am3359-cppi41";
|
|
reg = <0x0000 0x1000>,
|
|
<0x2000 0x1000>,
|
|
<0x3000 0x1000>,
|
|
<0x4000 0x4000>;
|
|
reg-names = "glue", "controller", "scheduler", "queuemgr";
|
|
interrupts = <17>;
|
|
interrupt-names = "glue";
|
|
#dma-cells = <2>;
|
|
#dma-channels = <30>;
|
|
#dma-requests = <256>;
|
|
};
|
|
};
|
|
|
|
ocmcram: sram@40300000 {
|
|
compatible = "mmio-sram";
|
|
reg = <0x40300000 0x10000>; /* 64k */
|
|
ranges = <0x0 0x40300000 0x10000>;
|
|
#address-cells = <1>;
|
|
#size-cells = <1>;
|
|
|
|
pm_sram_code: pm-code-sram@0 {
|
|
compatible = "ti,sram";
|
|
reg = <0x0 0x1000>;
|
|
protect-exec;
|
|
};
|
|
|
|
pm_sram_data: pm-data-sram@1000 {
|
|
compatible = "ti,sram";
|
|
reg = <0x1000 0x1000>;
|
|
pool;
|
|
};
|
|
};
|
|
|
|
emif: emif@4c000000 {
|
|
compatible = "ti,emif-am3352";
|
|
reg = <0x4c000000 0x1000000>;
|
|
ti,hwmods = "emif";
|
|
interrupts = <101>;
|
|
sram = <&pm_sram_code
|
|
&pm_sram_data>;
|
|
ti,no-idle;
|
|
};
|
|
|
|
gpmc: gpmc@50000000 {
|
|
compatible = "ti,am3352-gpmc";
|
|
ti,hwmods = "gpmc";
|
|
ti,no-idle-on-init;
|
|
reg = <0x50000000 0x2000>;
|
|
interrupts = <100>;
|
|
dmas = <&edma 52 0>;
|
|
dma-names = "rxtx";
|
|
gpmc,num-cs = <7>;
|
|
gpmc,num-waitpins = <2>;
|
|
#address-cells = <2>;
|
|
#size-cells = <1>;
|
|
interrupt-controller;
|
|
#interrupt-cells = <2>;
|
|
gpio-controller;
|
|
#gpio-cells = <2>;
|
|
status = "disabled";
|
|
};
|
|
|
|
sham_target: target-module@53100000 {
|
|
compatible = "ti,sysc-omap3-sham", "ti,sysc";
|
|
reg = <0x53100100 0x4>,
|
|
<0x53100110 0x4>,
|
|
<0x53100114 0x4>;
|
|
reg-names = "rev", "sysc", "syss";
|
|
ti,sysc-mask = <(SYSC_OMAP2_SOFTRESET |
|
|
SYSC_OMAP2_AUTOIDLE)>;
|
|
ti,sysc-sidle = <SYSC_IDLE_FORCE>,
|
|
<SYSC_IDLE_NO>,
|
|
<SYSC_IDLE_SMART>;
|
|
ti,syss-mask = <1>;
|
|
/* Domains (P, C): per_pwrdm, l3_clkdm */
|
|
clocks = <&l3_clkctrl AM3_L3_SHAM_CLKCTRL 0>;
|
|
clock-names = "fck";
|
|
#address-cells = <1>;
|
|
#size-cells = <1>;
|
|
ranges = <0x0 0x53100000 0x1000>;
|
|
|
|
sham: sham@0 {
|
|
compatible = "ti,omap4-sham";
|
|
reg = <0 0x200>;
|
|
interrupts = <109>;
|
|
dmas = <&edma 36 0>;
|
|
dma-names = "rx";
|
|
};
|
|
};
|
|
|
|
aes_target: target-module@53500000 {
|
|
compatible = "ti,sysc-omap2", "ti,sysc";
|
|
reg = <0x53500080 0x4>,
|
|
<0x53500084 0x4>,
|
|
<0x53500088 0x4>;
|
|
reg-names = "rev", "sysc", "syss";
|
|
ti,sysc-mask = <(SYSC_OMAP2_SOFTRESET |
|
|
SYSC_OMAP2_AUTOIDLE)>;
|
|
ti,sysc-sidle = <SYSC_IDLE_FORCE>,
|
|
<SYSC_IDLE_NO>,
|
|
<SYSC_IDLE_SMART>,
|
|
<SYSC_IDLE_SMART_WKUP>;
|
|
ti,syss-mask = <1>;
|
|
/* Domains (P, C): per_pwrdm, l3_clkdm */
|
|
clocks = <&l3_clkctrl AM3_L3_AES_CLKCTRL 0>;
|
|
clock-names = "fck";
|
|
#address-cells = <1>;
|
|
#size-cells = <1>;
|
|
ranges = <0x0 0x53500000 0x1000>;
|
|
|
|
aes: aes@0 {
|
|
compatible = "ti,omap4-aes";
|
|
reg = <0 0xa0>;
|
|
interrupts = <103>;
|
|
dmas = <&edma 6 0>,
|
|
<&edma 5 0>;
|
|
dma-names = "tx", "rx";
|
|
};
|
|
};
|
|
|
|
target-module@56000000 {
|
|
compatible = "ti,sysc-omap4", "ti,sysc";
|
|
reg = <0x5600fe00 0x4>,
|
|
<0x5600fe10 0x4>;
|
|
reg-names = "rev", "sysc";
|
|
ti,sysc-midle = <SYSC_IDLE_FORCE>,
|
|
<SYSC_IDLE_NO>,
|
|
<SYSC_IDLE_SMART>;
|
|
ti,sysc-sidle = <SYSC_IDLE_FORCE>,
|
|
<SYSC_IDLE_NO>,
|
|
<SYSC_IDLE_SMART>;
|
|
clocks = <&gfx_l3_clkctrl AM3_GFX_L3_GFX_CLKCTRL 0>;
|
|
clock-names = "fck";
|
|
resets = <&prm_gfx 0>;
|
|
reset-names = "rstctrl";
|
|
#address-cells = <1>;
|
|
#size-cells = <1>;
|
|
ranges = <0 0x56000000 0x1000000>;
|
|
|
|
/*
|
|
* Closed source PowerVR driver, no child device
|
|
* binding or driver in mainline
|
|
*/
|
|
};
|
|
};
|
|
};
|
|
|
|
#include "am33xx-l4.dtsi"
|
|
#include "am33xx-clocks.dtsi"
|
|
|
|
&prcm {
|
|
prm_per: prm@c00 {
|
|
compatible = "ti,am3-prm-inst", "ti,omap-prm-inst";
|
|
reg = <0xc00 0x100>;
|
|
#reset-cells = <1>;
|
|
};
|
|
|
|
prm_wkup: prm@d00 {
|
|
compatible = "ti,am3-prm-inst", "ti,omap-prm-inst";
|
|
reg = <0xd00 0x100>;
|
|
#reset-cells = <1>;
|
|
};
|
|
|
|
prm_device: prm@f00 {
|
|
compatible = "ti,am3-prm-inst", "ti,omap-prm-inst";
|
|
reg = <0xf00 0x100>;
|
|
#reset-cells = <1>;
|
|
};
|
|
|
|
prm_gfx: prm@1100 {
|
|
compatible = "ti,am3-prm-inst", "ti,omap-prm-inst";
|
|
reg = <0x1100 0x100>;
|
|
#reset-cells = <1>;
|
|
};
|
|
};
|