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https://github.com/AuxXxilium/linux_dsm_epyc7002.git
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41ceeb5fef
This patch adds Z2 clock divider support for R-Car Gen3 SoC. Signed-off-by: Takeshi Kihara <takeshi.kihara.df@renesas.com> Signed-off-by: Simon Horman <horms+renesas@verge.net.au> Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
55 lines
1.4 KiB
C
55 lines
1.4 KiB
C
/*
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* R-Car Gen3 Clock Pulse Generator
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*
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* Copyright (C) 2015-2016 Glider bvba
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; version 2 of the License.
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*/
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#ifndef __CLK_RENESAS_RCAR_GEN3_CPG_H__
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#define __CLK_RENESAS_RCAR_GEN3_CPG_H__
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enum rcar_gen3_clk_types {
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CLK_TYPE_GEN3_MAIN = CLK_TYPE_CUSTOM,
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CLK_TYPE_GEN3_PLL0,
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CLK_TYPE_GEN3_PLL1,
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CLK_TYPE_GEN3_PLL2,
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CLK_TYPE_GEN3_PLL3,
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CLK_TYPE_GEN3_PLL4,
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CLK_TYPE_GEN3_SD,
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CLK_TYPE_GEN3_R,
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CLK_TYPE_GEN3_PE,
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CLK_TYPE_GEN3_Z,
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CLK_TYPE_GEN3_Z2,
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};
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#define DEF_GEN3_SD(_name, _id, _parent, _offset) \
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DEF_BASE(_name, _id, CLK_TYPE_GEN3_SD, _parent, .offset = _offset)
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#define DEF_GEN3_PE(_name, _id, _parent_sscg, _div_sscg, _parent_clean, \
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_div_clean) \
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DEF_BASE(_name, _id, CLK_TYPE_GEN3_PE, \
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(_parent_sscg) << 16 | (_parent_clean), \
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.div = (_div_sscg) << 16 | (_div_clean))
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struct rcar_gen3_cpg_pll_config {
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u8 extal_div;
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u8 pll1_mult;
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u8 pll1_div;
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u8 pll3_mult;
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u8 pll3_div;
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};
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#define CPG_RCKCR 0x240
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struct clk *rcar_gen3_cpg_clk_register(struct device *dev,
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const struct cpg_core_clk *core, const struct cpg_mssr_info *info,
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struct clk **clks, void __iomem *base,
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struct raw_notifier_head *notifiers);
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int rcar_gen3_cpg_init(const struct rcar_gen3_cpg_pll_config *config,
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unsigned int clk_extalr, u32 mode);
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#endif
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