mirror of
https://github.com/AuxXxilium/linux_dsm_epyc7002.git
synced 2024-12-22 19:43:07 +07:00
509 lines
13 KiB
C
509 lines
13 KiB
C
/*
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* Copyright 2010 Red Hat Inc.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
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* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
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* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
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* OTHER DEALINGS IN THE SOFTWARE.
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*
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* Authors: Ben Skeggs
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*/
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#include "drmP.h"
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#include "nouveau_drv.h"
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#include "nouveau_mm.h"
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static void nvc0_fifo_isr(struct drm_device *);
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struct nvc0_fifo_priv {
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struct nouveau_gpuobj *playlist[2];
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int cur_playlist;
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struct nouveau_vma user_vma;
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int spoon_nr;
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};
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struct nvc0_fifo_chan {
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struct nouveau_gpuobj *user;
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struct nouveau_gpuobj *ramfc;
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};
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static void
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nvc0_fifo_playlist_update(struct drm_device *dev)
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{
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struct drm_nouveau_private *dev_priv = dev->dev_private;
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struct nouveau_instmem_engine *pinstmem = &dev_priv->engine.instmem;
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struct nouveau_fifo_engine *pfifo = &dev_priv->engine.fifo;
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struct nvc0_fifo_priv *priv = pfifo->priv;
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struct nouveau_gpuobj *cur;
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int i, p;
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cur = priv->playlist[priv->cur_playlist];
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priv->cur_playlist = !priv->cur_playlist;
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for (i = 0, p = 0; i < 128; i++) {
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if (!(nv_rd32(dev, 0x3004 + (i * 8)) & 1))
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continue;
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nv_wo32(cur, p + 0, i);
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nv_wo32(cur, p + 4, 0x00000004);
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p += 8;
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}
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pinstmem->flush(dev);
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nv_wr32(dev, 0x002270, cur->vinst >> 12);
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nv_wr32(dev, 0x002274, 0x01f00000 | (p >> 3));
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if (!nv_wait(dev, 0x00227c, 0x00100000, 0x00000000))
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NV_ERROR(dev, "PFIFO - playlist update failed\n");
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}
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void
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nvc0_fifo_disable(struct drm_device *dev)
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{
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}
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void
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nvc0_fifo_enable(struct drm_device *dev)
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{
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}
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bool
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nvc0_fifo_reassign(struct drm_device *dev, bool enable)
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{
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return false;
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}
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bool
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nvc0_fifo_cache_pull(struct drm_device *dev, bool enable)
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{
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return false;
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}
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int
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nvc0_fifo_channel_id(struct drm_device *dev)
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{
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return 127;
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}
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int
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nvc0_fifo_create_context(struct nouveau_channel *chan)
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{
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struct drm_device *dev = chan->dev;
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struct drm_nouveau_private *dev_priv = dev->dev_private;
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struct nouveau_instmem_engine *pinstmem = &dev_priv->engine.instmem;
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struct nouveau_fifo_engine *pfifo = &dev_priv->engine.fifo;
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struct nvc0_fifo_priv *priv = pfifo->priv;
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struct nvc0_fifo_chan *fifoch;
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u64 ib_virt = chan->pushbuf_base + chan->dma.ib_base * 4;
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int ret;
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chan->fifo_priv = kzalloc(sizeof(*fifoch), GFP_KERNEL);
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if (!chan->fifo_priv)
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return -ENOMEM;
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fifoch = chan->fifo_priv;
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/* allocate vram for control regs, map into polling area */
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ret = nouveau_gpuobj_new(dev, NULL, 0x1000, 0x1000,
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NVOBJ_FLAG_ZERO_ALLOC, &fifoch->user);
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if (ret)
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goto error;
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nouveau_vm_map_at(&priv->user_vma, chan->id * 0x1000,
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*(struct nouveau_mem **)fifoch->user->node);
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chan->user = ioremap_wc(pci_resource_start(dev->pdev, 1) +
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priv->user_vma.offset + (chan->id * 0x1000),
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PAGE_SIZE);
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if (!chan->user) {
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ret = -ENOMEM;
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goto error;
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}
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/* ramfc */
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ret = nouveau_gpuobj_new_fake(dev, chan->ramin->pinst,
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chan->ramin->vinst, 0x100,
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NVOBJ_FLAG_ZERO_ALLOC, &fifoch->ramfc);
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if (ret)
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goto error;
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nv_wo32(fifoch->ramfc, 0x08, lower_32_bits(fifoch->user->vinst));
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nv_wo32(fifoch->ramfc, 0x0c, upper_32_bits(fifoch->user->vinst));
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nv_wo32(fifoch->ramfc, 0x10, 0x0000face);
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nv_wo32(fifoch->ramfc, 0x30, 0xfffff902);
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nv_wo32(fifoch->ramfc, 0x48, lower_32_bits(ib_virt));
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nv_wo32(fifoch->ramfc, 0x4c, drm_order(chan->dma.ib_max + 1) << 16 |
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upper_32_bits(ib_virt));
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nv_wo32(fifoch->ramfc, 0x54, 0x00000002);
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nv_wo32(fifoch->ramfc, 0x84, 0x20400000);
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nv_wo32(fifoch->ramfc, 0x94, 0x30000001);
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nv_wo32(fifoch->ramfc, 0x9c, 0x00000100);
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nv_wo32(fifoch->ramfc, 0xa4, 0x1f1f1f1f);
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nv_wo32(fifoch->ramfc, 0xa8, 0x1f1f1f1f);
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nv_wo32(fifoch->ramfc, 0xac, 0x0000001f);
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nv_wo32(fifoch->ramfc, 0xb8, 0xf8000000);
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nv_wo32(fifoch->ramfc, 0xf8, 0x10003080); /* 0x002310 */
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nv_wo32(fifoch->ramfc, 0xfc, 0x10000010); /* 0x002350 */
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pinstmem->flush(dev);
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nv_wr32(dev, 0x003000 + (chan->id * 8), 0xc0000000 |
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(chan->ramin->vinst >> 12));
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nv_wr32(dev, 0x003004 + (chan->id * 8), 0x001f0001);
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nvc0_fifo_playlist_update(dev);
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return 0;
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error:
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pfifo->destroy_context(chan);
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return ret;
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}
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void
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nvc0_fifo_destroy_context(struct nouveau_channel *chan)
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{
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struct drm_device *dev = chan->dev;
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struct nvc0_fifo_chan *fifoch;
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nv_mask(dev, 0x003004 + (chan->id * 8), 0x00000001, 0x00000000);
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nv_wr32(dev, 0x002634, chan->id);
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if (!nv_wait(dev, 0x0002634, 0xffffffff, chan->id))
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NV_WARN(dev, "0x2634 != chid: 0x%08x\n", nv_rd32(dev, 0x2634));
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nvc0_fifo_playlist_update(dev);
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nv_wr32(dev, 0x003000 + (chan->id * 8), 0x00000000);
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if (chan->user) {
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iounmap(chan->user);
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chan->user = NULL;
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}
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fifoch = chan->fifo_priv;
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chan->fifo_priv = NULL;
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if (!fifoch)
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return;
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nouveau_gpuobj_ref(NULL, &fifoch->ramfc);
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nouveau_gpuobj_ref(NULL, &fifoch->user);
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kfree(fifoch);
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}
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int
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nvc0_fifo_load_context(struct nouveau_channel *chan)
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{
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return 0;
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}
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int
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nvc0_fifo_unload_context(struct drm_device *dev)
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{
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int i;
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for (i = 0; i < 128; i++) {
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if (!(nv_rd32(dev, 0x003004 + (i * 8)) & 1))
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continue;
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nv_mask(dev, 0x003004 + (i * 8), 0x00000001, 0x00000000);
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nv_wr32(dev, 0x002634, i);
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if (!nv_wait(dev, 0x002634, 0xffffffff, i)) {
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NV_INFO(dev, "PFIFO: kick ch %d failed: 0x%08x\n",
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i, nv_rd32(dev, 0x002634));
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return -EBUSY;
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}
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}
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return 0;
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}
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static void
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nvc0_fifo_destroy(struct drm_device *dev)
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{
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struct drm_nouveau_private *dev_priv = dev->dev_private;
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struct nouveau_fifo_engine *pfifo = &dev_priv->engine.fifo;
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struct nvc0_fifo_priv *priv;
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priv = pfifo->priv;
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if (!priv)
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return;
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nouveau_vm_put(&priv->user_vma);
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nouveau_gpuobj_ref(NULL, &priv->playlist[1]);
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nouveau_gpuobj_ref(NULL, &priv->playlist[0]);
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kfree(priv);
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}
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void
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nvc0_fifo_takedown(struct drm_device *dev)
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{
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nv_wr32(dev, 0x002140, 0x00000000);
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nvc0_fifo_destroy(dev);
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}
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static int
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nvc0_fifo_create(struct drm_device *dev)
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{
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struct drm_nouveau_private *dev_priv = dev->dev_private;
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struct nouveau_fifo_engine *pfifo = &dev_priv->engine.fifo;
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struct nvc0_fifo_priv *priv;
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int ret;
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priv = kzalloc(sizeof(*priv), GFP_KERNEL);
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if (!priv)
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return -ENOMEM;
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pfifo->priv = priv;
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ret = nouveau_gpuobj_new(dev, NULL, 0x1000, 0x1000, 0,
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&priv->playlist[0]);
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if (ret)
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goto error;
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ret = nouveau_gpuobj_new(dev, NULL, 0x1000, 0x1000, 0,
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&priv->playlist[1]);
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if (ret)
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goto error;
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ret = nouveau_vm_get(dev_priv->bar1_vm, pfifo->channels * 0x1000,
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12, NV_MEM_ACCESS_RW, &priv->user_vma);
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if (ret)
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goto error;
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nouveau_irq_register(dev, 8, nvc0_fifo_isr);
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NVOBJ_CLASS(dev, 0x506e, SW); /* nvsw */
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return 0;
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error:
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nvc0_fifo_destroy(dev);
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return ret;
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}
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int
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nvc0_fifo_init(struct drm_device *dev)
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{
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struct drm_nouveau_private *dev_priv = dev->dev_private;
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struct nouveau_fifo_engine *pfifo = &dev_priv->engine.fifo;
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struct nouveau_channel *chan;
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struct nvc0_fifo_priv *priv;
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int ret, i;
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if (!pfifo->priv) {
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ret = nvc0_fifo_create(dev);
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if (ret)
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return ret;
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}
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priv = pfifo->priv;
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/* reset PFIFO, enable all available PSUBFIFO areas */
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nv_mask(dev, 0x000200, 0x00000100, 0x00000000);
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nv_mask(dev, 0x000200, 0x00000100, 0x00000100);
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nv_wr32(dev, 0x000204, 0xffffffff);
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nv_wr32(dev, 0x002204, 0xffffffff);
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priv->spoon_nr = hweight32(nv_rd32(dev, 0x002204));
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NV_DEBUG(dev, "PFIFO: %d subfifo(s)\n", priv->spoon_nr);
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/* assign engines to subfifos */
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if (priv->spoon_nr >= 3) {
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nv_wr32(dev, 0x002208, ~(1 << 0)); /* PGRAPH */
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nv_wr32(dev, 0x00220c, ~(1 << 1)); /* PVP */
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nv_wr32(dev, 0x002210, ~(1 << 1)); /* PPP */
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nv_wr32(dev, 0x002214, ~(1 << 1)); /* PBSP */
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nv_wr32(dev, 0x002218, ~(1 << 2)); /* PCE0 */
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nv_wr32(dev, 0x00221c, ~(1 << 1)); /* PCE1 */
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}
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/* PSUBFIFO[n] */
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for (i = 0; i < priv->spoon_nr; i++) {
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nv_mask(dev, 0x04013c + (i * 0x2000), 0x10000100, 0x00000000);
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nv_wr32(dev, 0x040108 + (i * 0x2000), 0xffffffff); /* INTR */
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nv_wr32(dev, 0x04010c + (i * 0x2000), 0xfffffeff); /* INTR_EN */
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}
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nv_mask(dev, 0x002200, 0x00000001, 0x00000001);
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nv_wr32(dev, 0x002254, 0x10000000 | priv->user_vma.offset >> 12);
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nv_wr32(dev, 0x002a00, 0xffffffff); /* clears PFIFO.INTR bit 30 */
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nv_wr32(dev, 0x002100, 0xffffffff);
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nv_wr32(dev, 0x002140, 0xbfffffff);
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/* restore PFIFO context table */
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for (i = 0; i < 128; i++) {
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chan = dev_priv->channels.ptr[i];
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if (!chan || !chan->fifo_priv)
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continue;
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nv_wr32(dev, 0x003000 + (i * 8), 0xc0000000 |
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(chan->ramin->vinst >> 12));
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nv_wr32(dev, 0x003004 + (i * 8), 0x001f0001);
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}
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nvc0_fifo_playlist_update(dev);
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return 0;
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}
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struct nouveau_enum nvc0_fifo_fault_unit[] = {
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{ 0x00, "PGRAPH" },
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{ 0x03, "PEEPHOLE" },
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{ 0x04, "BAR1" },
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{ 0x05, "BAR3" },
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{ 0x07, "PFIFO" },
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{ 0x10, "PBSP" },
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{ 0x11, "PPPP" },
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{ 0x13, "PCOUNTER" },
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{ 0x14, "PVP" },
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{ 0x15, "PCOPY0" },
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{ 0x16, "PCOPY1" },
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{ 0x17, "PDAEMON" },
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{}
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};
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struct nouveau_enum nvc0_fifo_fault_reason[] = {
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{ 0x00, "PT_NOT_PRESENT" },
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{ 0x01, "PT_TOO_SHORT" },
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{ 0x02, "PAGE_NOT_PRESENT" },
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{ 0x03, "VM_LIMIT_EXCEEDED" },
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{ 0x04, "NO_CHANNEL" },
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{ 0x05, "PAGE_SYSTEM_ONLY" },
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{ 0x06, "PAGE_READ_ONLY" },
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{ 0x0a, "COMPRESSED_SYSRAM" },
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{ 0x0c, "INVALID_STORAGE_TYPE" },
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{}
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};
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struct nouveau_enum nvc0_fifo_fault_hubclient[] = {
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{ 0x01, "PCOPY0" },
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{ 0x02, "PCOPY1" },
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{ 0x04, "DISPATCH" },
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{ 0x05, "CTXCTL" },
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{ 0x06, "PFIFO" },
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{ 0x07, "BAR_READ" },
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{ 0x08, "BAR_WRITE" },
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{ 0x0b, "PVP" },
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{ 0x0c, "PPPP" },
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{ 0x0d, "PBSP" },
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{ 0x11, "PCOUNTER" },
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{ 0x12, "PDAEMON" },
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{ 0x14, "CCACHE" },
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{ 0x15, "CCACHE_POST" },
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{}
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};
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struct nouveau_enum nvc0_fifo_fault_gpcclient[] = {
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{ 0x01, "TEX" },
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{ 0x0c, "ESETUP" },
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{ 0x0e, "CTXCTL" },
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{ 0x0f, "PROP" },
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{}
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};
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struct nouveau_bitfield nvc0_fifo_subfifo_intr[] = {
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/* { 0x00008000, "" } seen with null ib push */
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{ 0x00200000, "ILLEGAL_MTHD" },
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{ 0x00800000, "EMPTY_SUBC" },
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{}
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};
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static void
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nvc0_fifo_isr_vm_fault(struct drm_device *dev, int unit)
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{
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u32 inst = nv_rd32(dev, 0x2800 + (unit * 0x10));
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u32 valo = nv_rd32(dev, 0x2804 + (unit * 0x10));
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u32 vahi = nv_rd32(dev, 0x2808 + (unit * 0x10));
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u32 stat = nv_rd32(dev, 0x280c + (unit * 0x10));
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u32 client = (stat & 0x00001f00) >> 8;
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NV_INFO(dev, "PFIFO: %s fault at 0x%010llx [",
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(stat & 0x00000080) ? "write" : "read", (u64)vahi << 32 | valo);
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nouveau_enum_print(nvc0_fifo_fault_reason, stat & 0x0000000f);
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printk("] from ");
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nouveau_enum_print(nvc0_fifo_fault_unit, unit);
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if (stat & 0x00000040) {
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printk("/");
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nouveau_enum_print(nvc0_fifo_fault_hubclient, client);
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} else {
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printk("/GPC%d/", (stat & 0x1f000000) >> 24);
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nouveau_enum_print(nvc0_fifo_fault_gpcclient, client);
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}
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printk(" on channel 0x%010llx\n", (u64)inst << 12);
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}
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static void
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nvc0_fifo_isr_subfifo_intr(struct drm_device *dev, int unit)
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{
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u32 stat = nv_rd32(dev, 0x040108 + (unit * 0x2000));
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u32 addr = nv_rd32(dev, 0x0400c0 + (unit * 0x2000));
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u32 data = nv_rd32(dev, 0x0400c4 + (unit * 0x2000));
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u32 chid = nv_rd32(dev, 0x040120 + (unit * 0x2000)) & 0x7f;
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u32 subc = (addr & 0x00070000);
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u32 mthd = (addr & 0x00003ffc);
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NV_INFO(dev, "PSUBFIFO %d:", unit);
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nouveau_bitfield_print(nvc0_fifo_subfifo_intr, stat);
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NV_INFO(dev, "PSUBFIFO %d: ch %d subc %d mthd 0x%04x data 0x%08x\n",
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unit, chid, subc, mthd, data);
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nv_wr32(dev, 0x0400c0 + (unit * 0x2000), 0x80600008);
|
|
nv_wr32(dev, 0x040108 + (unit * 0x2000), stat);
|
|
}
|
|
|
|
static void
|
|
nvc0_fifo_isr(struct drm_device *dev)
|
|
{
|
|
u32 stat = nv_rd32(dev, 0x002100);
|
|
|
|
if (stat & 0x00000100) {
|
|
NV_INFO(dev, "PFIFO: unknown status 0x00000100\n");
|
|
nv_wr32(dev, 0x002100, 0x00000100);
|
|
stat &= ~0x00000100;
|
|
}
|
|
|
|
if (stat & 0x10000000) {
|
|
u32 units = nv_rd32(dev, 0x00259c);
|
|
u32 u = units;
|
|
|
|
while (u) {
|
|
int i = ffs(u) - 1;
|
|
nvc0_fifo_isr_vm_fault(dev, i);
|
|
u &= ~(1 << i);
|
|
}
|
|
|
|
nv_wr32(dev, 0x00259c, units);
|
|
stat &= ~0x10000000;
|
|
}
|
|
|
|
if (stat & 0x20000000) {
|
|
u32 units = nv_rd32(dev, 0x0025a0);
|
|
u32 u = units;
|
|
|
|
while (u) {
|
|
int i = ffs(u) - 1;
|
|
nvc0_fifo_isr_subfifo_intr(dev, i);
|
|
u &= ~(1 << i);
|
|
}
|
|
|
|
nv_wr32(dev, 0x0025a0, units);
|
|
stat &= ~0x20000000;
|
|
}
|
|
|
|
if (stat & 0x40000000) {
|
|
NV_INFO(dev, "PFIFO: unknown status 0x40000000\n");
|
|
nv_mask(dev, 0x002a00, 0x00000000, 0x00000000);
|
|
stat &= ~0x40000000;
|
|
}
|
|
|
|
if (stat) {
|
|
NV_INFO(dev, "PFIFO: unhandled status 0x%08x\n", stat);
|
|
nv_wr32(dev, 0x002100, stat);
|
|
nv_wr32(dev, 0x002140, 0);
|
|
}
|
|
}
|