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https://github.com/AuxXxilium/linux_dsm_epyc7002.git
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947bf103fc
This helps remove asid-to-mm reverse map While mm->context.id contains the ASID assigned to a process, our ASID allocator also used asid_mm_map[] reverse map. In a new allocation cycle (mm->ASID >= @asid_cache), the Round Robin ASID allocator used this to check if new @asid_cache belonged to some mm2 (from prev cycle). If so, it could locate that mm using the ASID reverse map, and mark that mm as unallocated ASID, to force it to refresh at the time of switch_mm() However, for SMP, the reverse map has to be maintained per CPU, so becomes 2 dimensional, hence got rid of it. With reverse map gone, it is NOT possible to reach out to current assignee. So we track the ASID allocation generation/cycle and on every switch_mm(), check if the current generation of CPU ASID is same as mm's ASID; If not it is refreshed. (Based loosely on arch/sh implementation) Signed-off-by: Vineet Gupta <vgupta@synopsys.com>
387 lines
12 KiB
ArmAsm
387 lines
12 KiB
ArmAsm
/*
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* TLB Exception Handling for ARC
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*
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* Copyright (C) 2004, 2007-2010, 2011-2012 Synopsys, Inc. (www.synopsys.com)
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*
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* Vineetg: April 2011 :
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* -MMU v1: moved out legacy code into a seperate file
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* -MMU v3: PD{0,1} bits layout changed: They don't overlap anymore,
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* helps avoid a shift when preparing PD0 from PTE
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*
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* Vineetg: July 2009
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* -For MMU V2, we need not do heuristics at the time of commiting a D-TLB
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* entry, so that it doesn't knock out it's I-TLB entry
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* -Some more fine tuning:
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* bmsk instead of add, asl.cc instead of branch, delay slot utilise etc
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*
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* Vineetg: July 2009
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* -Practically rewrote the I/D TLB Miss handlers
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* Now 40 and 135 instructions a peice as compared to 131 and 449 resp.
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* Hence Leaner by 1.5 K
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* Used Conditional arithmetic to replace excessive branching
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* Also used short instructions wherever possible
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*
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* Vineetg: Aug 13th 2008
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* -Passing ECR (Exception Cause REG) to do_page_fault( ) for printing
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* more information in case of a Fatality
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*
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* Vineetg: March 25th Bug #92690
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* -Added Debug Code to check if sw-ASID == hw-ASID
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* Rahul Trivedi, Amit Bhor: Codito Technologies 2004
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*/
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.cpu A7
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#include <linux/linkage.h>
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#include <asm/entry.h>
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#include <asm/mmu.h>
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#include <asm/pgtable.h>
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#include <asm/arcregs.h>
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#include <asm/cache.h>
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#include <asm/processor.h>
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#include <asm/tlb-mmu1.h>
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;-----------------------------------------------------------------
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; ARC700 Exception Handling doesn't auto-switch stack and it only provides
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; ONE scratch AUX reg "ARC_REG_SCRATCH_DATA0"
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;
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; For Non-SMP, the scratch AUX reg is repurposed to cache task PGD, so a
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; "global" is used to free-up FIRST core reg to be able to code the rest of
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; exception prologue (IRQ auto-disabled on Exceptions, so it's IRQ-safe).
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; Since the Fast Path TLB Miss handler is coded with 4 regs, the remaining 3
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; need to be saved as well by extending the "global" to be 4 words. Hence
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; ".size ex_saved_reg1, 16"
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; [All of this dance is to avoid stack switching for each TLB Miss, since we
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; only need to save only a handful of regs, as opposed to complete reg file]
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;
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; For ARC700 SMP, the "global" obviously can't be used for free up the FIRST
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; core reg as it will not be SMP safe.
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; Thus scratch AUX reg is used (and no longer used to cache task PGD).
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; To save the rest of 3 regs - per cpu, the global is made "per-cpu".
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; Epilogue thus has to locate the "per-cpu" storage for regs.
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; To avoid cache line bouncing the per-cpu global is aligned/sized per
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; L1_CACHE_SHIFT, despite fundamentally needing to be 12 bytes only. Hence
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; ".size ex_saved_reg1, (CONFIG_NR_CPUS << L1_CACHE_SHIFT)"
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; As simple as that....
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;--------------------------------------------------------------------------
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; scratch memory to save [r0-r3] used to code TLB refill Handler
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ARCFP_DATA ex_saved_reg1
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.align 1 << L1_CACHE_SHIFT
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.type ex_saved_reg1, @object
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#ifdef CONFIG_SMP
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.size ex_saved_reg1, (CONFIG_NR_CPUS << L1_CACHE_SHIFT)
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ex_saved_reg1:
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.zero (CONFIG_NR_CPUS << L1_CACHE_SHIFT)
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#else
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.size ex_saved_reg1, 16
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ex_saved_reg1:
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.zero 16
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#endif
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.macro TLBMISS_FREEUP_REGS
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#ifdef CONFIG_SMP
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sr r0, [ARC_REG_SCRATCH_DATA0] ; freeup r0 to code with
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GET_CPU_ID r0 ; get to per cpu scratch mem,
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lsl r0, r0, L1_CACHE_SHIFT ; cache line wide per cpu
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add r0, @ex_saved_reg1, r0
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#else
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st r0, [@ex_saved_reg1]
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mov_s r0, @ex_saved_reg1
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#endif
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st_s r1, [r0, 4]
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st_s r2, [r0, 8]
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st_s r3, [r0, 12]
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; VERIFY if the ASID in MMU-PID Reg is same as
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; one in Linux data structures
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tlb_paranoid_check_asm
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.endm
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.macro TLBMISS_RESTORE_REGS
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#ifdef CONFIG_SMP
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GET_CPU_ID r0 ; get to per cpu scratch mem
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lsl r0, r0, L1_CACHE_SHIFT ; each is cache line wide
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add r0, @ex_saved_reg1, r0
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ld_s r3, [r0,12]
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ld_s r2, [r0, 8]
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ld_s r1, [r0, 4]
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lr r0, [ARC_REG_SCRATCH_DATA0]
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#else
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mov_s r0, @ex_saved_reg1
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ld_s r3, [r0,12]
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ld_s r2, [r0, 8]
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ld_s r1, [r0, 4]
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ld_s r0, [r0]
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#endif
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.endm
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;============================================================================
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; Troubleshooting Stuff
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;============================================================================
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; Linux keeps ASID (Address Space ID) in task->active_mm->context.asid
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; When Creating TLB Entries, instead of doing 3 dependent loads from memory,
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; we use the MMU PID Reg to get current ASID.
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; In bizzare scenrios SW and HW ASID can get out-of-sync which is trouble.
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; So we try to detect this in TLB Mis shandler
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.macro tlb_paranoid_check_asm
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#ifdef CONFIG_ARC_DBG_TLB_PARANOIA
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GET_CURR_TASK_ON_CPU r3
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ld r0, [r3, TASK_ACT_MM]
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ld r0, [r0, MM_CTXT+MM_CTXT_ASID]
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breq r0, 0, 55f ; Error if no ASID allocated
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lr r1, [ARC_REG_PID]
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and r1, r1, 0xFF
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and r2, r0, 0xFF ; MMU PID bits only for comparison
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breq r1, r2, 5f
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55:
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; Error if H/w and S/w ASID don't match, but NOT if in kernel mode
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lr r2, [erstatus]
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bbit0 r2, STATUS_U_BIT, 5f
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; We sure are in troubled waters, Flag the error, but to do so
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; need to switch to kernel mode stack to call error routine
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GET_TSK_STACK_BASE r3, sp
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; Call printk to shoutout aloud
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mov r2, 1
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j print_asid_mismatch
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5: ; ASIDs match so proceed normally
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nop
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#endif
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.endm
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;============================================================================
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;TLB Miss handling Code
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;============================================================================
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;-----------------------------------------------------------------------------
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; This macro does the page-table lookup for the faulting address.
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; OUT: r0 = PTE faulted on, r1 = ptr to PTE, r2 = Faulting V-address
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.macro LOAD_FAULT_PTE
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lr r2, [efa]
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#ifndef CONFIG_SMP
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lr r1, [ARC_REG_SCRATCH_DATA0] ; current pgd
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#else
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GET_CURR_TASK_ON_CPU r1
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ld r1, [r1, TASK_ACT_MM]
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ld r1, [r1, MM_PGD]
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#endif
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lsr r0, r2, PGDIR_SHIFT ; Bits for indexing into PGD
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ld.as r1, [r1, r0] ; PGD entry corresp to faulting addr
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and.f r1, r1, PAGE_MASK ; Ignoring protection and other flags
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; contains Ptr to Page Table
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bz.d do_slow_path_pf ; if no Page Table, do page fault
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; Get the PTE entry: The idea is
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; (1) x = addr >> PAGE_SHIFT -> masks page-off bits from @fault-addr
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; (2) y = x & (PTRS_PER_PTE - 1) -> to get index
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; (3) z = pgtbl[y]
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; To avoid the multiply by in end, we do the -2, <<2 below
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lsr r0, r2, (PAGE_SHIFT - 2)
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and r0, r0, ( (PTRS_PER_PTE - 1) << 2)
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ld.aw r0, [r1, r0] ; get PTE and PTE ptr for fault addr
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#ifdef CONFIG_ARC_DBG_TLB_MISS_COUNT
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and.f 0, r0, _PAGE_PRESENT
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bz 1f
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ld r3, [num_pte_not_present]
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add r3, r3, 1
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st r3, [num_pte_not_present]
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1:
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#endif
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.endm
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;-----------------------------------------------------------------
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; Convert Linux PTE entry into TLB entry
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; A one-word PTE entry is programmed as two-word TLB Entry [PD0:PD1] in mmu
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; IN: r0 = PTE, r1 = ptr to PTE
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.macro CONV_PTE_TO_TLB
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and r3, r0, PTE_BITS_RWX ; r w x
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lsl r2, r3, 3 ; r w x 0 0 0
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and.f 0, r0, _PAGE_GLOBAL
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or.z r2, r2, r3 ; r w x r w x
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and r3, r0, PTE_BITS_NON_RWX_IN_PD1 ; Extract PFN+cache bits from PTE
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or r3, r3, r2
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sr r3, [ARC_REG_TLBPD1] ; these go in PD1
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and r2, r0, PTE_BITS_IN_PD0 ; Extract other PTE flags: (V)alid, (G)lb
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lr r3,[ARC_REG_TLBPD0] ; MMU prepares PD0 with vaddr and asid
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or r3, r3, r2 ; S | vaddr | {sasid|asid}
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sr r3,[ARC_REG_TLBPD0] ; rewrite PD0
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.endm
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;-----------------------------------------------------------------
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; Commit the TLB entry into MMU
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.macro COMMIT_ENTRY_TO_MMU
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/* Get free TLB slot: Set = computed from vaddr, way = random */
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sr TLBGetIndex, [ARC_REG_TLBCOMMAND]
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/* Commit the Write */
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#if (CONFIG_ARC_MMU_VER >= 2) /* introduced in v2 */
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sr TLBWriteNI, [ARC_REG_TLBCOMMAND]
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#else
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sr TLBWrite, [ARC_REG_TLBCOMMAND]
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#endif
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.endm
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ARCFP_CODE ;Fast Path Code, candidate for ICCM
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;-----------------------------------------------------------------------------
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; I-TLB Miss Exception Handler
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;-----------------------------------------------------------------------------
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ARC_ENTRY EV_TLBMissI
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TLBMISS_FREEUP_REGS
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#ifdef CONFIG_ARC_DBG_TLB_MISS_COUNT
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ld r0, [@numitlb]
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add r0, r0, 1
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st r0, [@numitlb]
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#endif
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;----------------------------------------------------------------
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; Get the PTE corresponding to V-addr accessed, r2 is setup with EFA
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LOAD_FAULT_PTE
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;----------------------------------------------------------------
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; VERIFY_PTE: Check if PTE permissions approp for executing code
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cmp_s r2, VMALLOC_START
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mov_s r2, (_PAGE_PRESENT | _PAGE_EXECUTE)
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or.hs r2, r2, _PAGE_GLOBAL
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and r3, r0, r2 ; Mask out NON Flag bits from PTE
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xor.f r3, r3, r2 ; check ( ( pte & flags_test ) == flags_test )
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bnz do_slow_path_pf
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; Let Linux VM know that the page was accessed
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or r0, r0, _PAGE_ACCESSED ; set Accessed Bit
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st_s r0, [r1] ; Write back PTE
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CONV_PTE_TO_TLB
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COMMIT_ENTRY_TO_MMU
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TLBMISS_RESTORE_REGS
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rtie
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ARC_EXIT EV_TLBMissI
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;-----------------------------------------------------------------------------
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; D-TLB Miss Exception Handler
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;-----------------------------------------------------------------------------
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ARC_ENTRY EV_TLBMissD
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TLBMISS_FREEUP_REGS
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#ifdef CONFIG_ARC_DBG_TLB_MISS_COUNT
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ld r0, [@numdtlb]
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add r0, r0, 1
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st r0, [@numdtlb]
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#endif
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;----------------------------------------------------------------
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; Get the PTE corresponding to V-addr accessed
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; If PTE exists, it will setup, r0 = PTE, r1 = Ptr to PTE, r2 = EFA
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LOAD_FAULT_PTE
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;----------------------------------------------------------------
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; VERIFY_PTE: Chk if PTE permissions approp for data access (R/W/R+W)
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cmp_s r2, VMALLOC_START
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mov_s r2, _PAGE_PRESENT ; common bit for K/U PTE
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or.hs r2, r2, _PAGE_GLOBAL ; kernel PTE only
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; Linux PTE [RWX] bits are semantically overloaded:
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; -If PAGE_GLOBAL set, they refer to kernel-only flags (vmalloc)
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; -Otherwise they are user-mode permissions, and those are exactly
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; same for kernel mode as well (e.g. copy_(to|from)_user)
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lr r3, [ecr]
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btst_s r3, ECR_C_BIT_DTLB_LD_MISS ; Read Access
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or.nz r2, r2, _PAGE_READ ; chk for Read flag in PTE
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btst_s r3, ECR_C_BIT_DTLB_ST_MISS ; Write Access
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or.nz r2, r2, _PAGE_WRITE ; chk for Write flag in PTE
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; Above laddering takes care of XCHG access (both R and W)
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; By now, r2 setup with all the Flags we need to check in PTE
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and r3, r0, r2 ; Mask out NON Flag bits from PTE
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brne.d r3, r2, do_slow_path_pf ; is ((pte & flags_test) == flags_test)
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;----------------------------------------------------------------
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; UPDATE_PTE: Let Linux VM know that page was accessed/dirty
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lr r3, [ecr]
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or r0, r0, _PAGE_ACCESSED ; Accessed bit always
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btst_s r3, ECR_C_BIT_DTLB_ST_MISS ; See if it was a Write Access ?
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or.nz r0, r0, _PAGE_MODIFIED ; if Write, set Dirty bit as well
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st_s r0, [r1] ; Write back PTE
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CONV_PTE_TO_TLB
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#if (CONFIG_ARC_MMU_VER == 1)
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; MMU with 2 way set assoc J-TLB, needs some help in pathetic case of
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; memcpy where 3 parties contend for 2 ways, ensuing a livelock.
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; But only for old MMU or one with Metal Fix
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TLB_WRITE_HEURISTICS
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#endif
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COMMIT_ENTRY_TO_MMU
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TLBMISS_RESTORE_REGS
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rtie
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;-------- Common routine to call Linux Page Fault Handler -----------
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do_slow_path_pf:
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; Restore the 4-scratch regs saved by fast path miss handler
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TLBMISS_RESTORE_REGS
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; Slow path TLB Miss handled as a regular ARC Exception
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; (stack switching / save the complete reg-file).
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EXCEPTION_PROLOGUE
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; ------- setup args for Linux Page fault Hanlder ---------
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mov_s r0, sp
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lr r1, [efa]
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; We don't want exceptions to be disabled while the fault is handled.
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; Now that we have saved the context we return from exception hence
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; exceptions get re-enable
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FAKE_RET_FROM_EXCPN r9
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bl do_page_fault
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b ret_from_exception
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ARC_EXIT EV_TLBMissD
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ARC_ENTRY EV_TLBMissB ; Bogus entry to measure sz of DTLBMiss hdlr
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